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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F08%3A03142089%21RIV09-MSM-21230___
rdf:type
n12:Vysledek skos:Concept
dcterms:description
This paper presents a scheduling technique used to optimize computation speed of loops running on architectures that may include pipelined dedicated processors. The problem under consideration is to find an optimal periodic schedule satisfying the timing constraints. Motivated by FPGA (Field-Programmable Gate Array) architecture we formulate a problem of cyclic scheduling on one dedicated processor where tasks are constrained by the precedence delays. Further we generalize this result to the set of dedicated processors. We also show how the set of constraints in both problems can be extended by start time related deadlines, multiprocessor tasks, changeover times and minimization of data transfers. We prove that this problem is NP-hard by reduction from Bratley's scheduling problem 1|rj,~dj|Cmax and we suggest a solution based on ILP (Integer Linear Programming) that allows one to minimize the completion time. This paper presents a scheduling technique used to optimize computation speed of loops running on architectures that may include pipelined dedicated processors. The problem under consideration is to find an optimal periodic schedule satisfying the timing constraints. Motivated by FPGA (Field-Programmable Gate Array) architecture we formulate a problem of cyclic scheduling on one dedicated processor where tasks are constrained by the precedence delays. Further we generalize this result to the set of dedicated processors. We also show how the set of constraints in both problems can be extended by start time related deadlines, multiprocessor tasks, changeover times and minimization of data transfers. We prove that this problem is NP-hard by reduction from Bratley's scheduling problem 1|rj,~dj|Cmax and we suggest a solution based on ILP (Integer Linear Programming) that allows one to minimize the completion time. Tento článek se zabývá rozvrhováním výpočetních smyček prováděných na HW architekturách obsahující pipelinované dedikované jednotky (např. FPGA). Problém je řešen pomocí celočíselného lineárního programování a výsledky jsou ukázány jak na standardních testovacích instancích, tak i vybrané aplikaci.
dcterms:title
Deadline Constrained Cyclic Scheduling on Pipelined Dedicated Processors Considering Multiprocessor Tasks and Changeover Times Deadline Constrained Cyclic Scheduling on Pipelined Dedicated Processors Considering Multiprocessor Tasks and Changeover Times Cyklické rozvrhování na dedikovaných procesorech uvažující multiprocesorové úlohy a časy na změnu nastavení procesoru
skos:prefLabel
Deadline Constrained Cyclic Scheduling on Pipelined Dedicated Processors Considering Multiprocessor Tasks and Changeover Times Cyklické rozvrhování na dedikovaných procesorech uvažující multiprocesorové úlohy a časy na změnu nastavení procesoru Deadline Constrained Cyclic Scheduling on Pipelined Dedicated Processors Considering Multiprocessor Tasks and Changeover Times
skos:notation
RIV/68407700:21230/08:03142089!RIV09-MSM-21230___
n4:aktivita
n9:Z
n4:aktivity
Z(MSM6840770038)
n4:cisloPeriodika
9-10
n4:dodaniDat
n7:2009
n4:domaciTvurceVysledku
n11:5834805 n11:7678436
n4:druhVysledku
n14:J
n4:duvernostUdaju
n13:S
n4:entitaPredkladatele
n8:predkladatel
n4:idSjednocenehoVysledku
362240
n4:idVysledku
RIV/68407700:21230/08:03142089
n4:jazykVysledku
n17:eng
n4:klicovaSlova
Changeover times; FPGA; High-level synthesis; Integer linear programming
n4:klicoveSlovo
n10:Integer%20linear%20programming n10:FPGA n10:High-level%20synthesis n10:Changeover%20times
n4:kodStatuVydavatele
NL - Nizozemsko
n4:kontrolniKodProRIV
[A45E41EB2376]
n4:nazevZdroje
Mathematical and Computer Modelling
n4:obor
n16:BB
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:rokUplatneniVysledku
n7:2008
n4:svazekPeriodika
47
n4:tvurceVysledku
Hanzálek, Zdeněk Šůcha, Přemysl
n4:wos
000255511900011
n4:zamer
n18:MSM6840770038
s:issn
0895-7177
s:numberOfPages
18
n15:organizacniJednotka
21230