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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F08%3A00147000%21RIV10-MSM-21230___
rdf:type
skos:Concept n9:Vysledek
dcterms:description
The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-Up-Tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture. The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-Up-Tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture.
dcterms:title
Experimental SEU Impact on Digital Design Implemented in FPGAs Experimental SEU Impact on Digital Design Implemented in FPGAs
skos:prefLabel
Experimental SEU Impact on Digital Design Implemented in FPGAs Experimental SEU Impact on Digital Design Implemented in FPGAs
skos:notation
RIV/68407700:21230/08:00147000!RIV10-MSM-21230___
n3:aktivita
n8:P n8:Z
n3:aktivity
P(FI-IM4/149), Z(MSM6840770014)
n3:dodaniDat
n10:2010
n3:domaciTvurceVysledku
n7:7140827 n7:7205651
n3:druhVysledku
n4:D
n3:duvernostUdaju
n11:S
n3:entitaPredkladatele
n22:predkladatel
n3:idSjednocenehoVysledku
367225
n3:idVysledku
RIV/68407700:21230/08:00147000
n3:jazykVysledku
n18:eng
n3:klicovaSlova
FPGA; dependability; fault emulator; fault model; single event upset
n3:klicoveSlovo
n12:dependability n12:FPGA n12:single%20event%20upset n12:fault%20emulator n12:fault%20model
n3:kontrolniKodProRIV
[FD43EA1E8609]
n3:mistoKonaniAkce
Parma
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings of 11th Euromicro Conference on Digital System Design
n3:obor
n13:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
3
n3:projekt
n17:FI-IM4%2F149
n3:rokUplatneniVysledku
n10:2008
n3:tvurceVysledku
Kubátová, Hana Kubalík, Pavel
n3:typAkce
n20:WRD
n3:wos
000264279400014
n3:zahajeniAkce
2008-09-03+02:00
n3:zamer
n15:MSM6840770014
s:numberOfPages
4
n21:hasPublisher
IEEE Computer Society
n16:isbn
978-0-7695-3277-6
n14:organizacniJednotka
21230