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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F08%3A00145451%21RIV10-MSM-21230___
rdf:type
n20:Vysledek skos:Concept
dcterms:description
We propose a method to efficiently design a %22parity generator%22, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system. We propose a method to efficiently design a %22parity generator%22, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system.
dcterms:title
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
skos:prefLabel
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
skos:notation
RIV/68407700:21230/08:00145451!RIV10-MSM-21230___
n3:aktivita
n18:P n18:Z
n3:aktivity
P(FI-IM4/149), Z(MSM6840770014)
n3:dodaniDat
n8:2010
n3:domaciTvurceVysledku
n5:7140827 n5:2194937 n5:7205651
n3:druhVysledku
n13:D
n3:duvernostUdaju
n21:S
n3:entitaPredkladatele
n4:predkladatel
n3:idSjednocenehoVysledku
355644
n3:idVysledku
RIV/68407700:21230/08:00145451
n3:jazykVysledku
n15:eng
n3:klicovaSlova
FC-Min; On-line testing; Output grouping; Parity prediction
n3:klicoveSlovo
n11:On-line%20testing n11:Output%20grouping n11:Parity%20prediction n11:FC-Min
n3:kontrolniKodProRIV
[D7607BF31444]
n3:mistoKonaniAkce
Parma
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings of 11th Euromicro Conference on Digital System Design
n3:obor
n6:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n16:FI-IM4%2F149
n3:rokUplatneniVysledku
n8:2008
n3:tvurceVysledku
Kubalík, Pavel Kubátová, Hana Fišer, Petr
n3:typAkce
n22:WRD
n3:zahajeniAkce
2008-09-03+02:00
n3:zamer
n14:MSM6840770014
s:numberOfPages
4
n17:hasPublisher
IEEE Computer Society
n12:isbn
978-0-7695-3277-6
n10:organizacniJednotka
21230