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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F07%3A03130529%21RIV08-MSM-21230___
rdf:type
n6:Vysledek skos:Concept
dcterms:description
Popis metody injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám. The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed. The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed.
dcterms:title
Injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
skos:prefLabel
Injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
skos:notation
RIV/68407700:21230/07:03130529!RIV08-MSM-21230___
n3:strany
357;360
n3:aktivita
n7:Z
n3:aktivity
Z(MSM6840770014)
n3:dodaniDat
n13:2008
n3:domaciTvurceVysledku
n8:7205651 n8:7140827 n8:5680182
n3:druhVysledku
n18:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n15:predkladatel
n3:idSjednocenehoVysledku
421744
n3:idVysledku
RIV/68407700:21230/07:03130529
n3:jazykVysledku
n16:eng
n3:klicovaSlova
hardware fault emulation, fault tolerant design, digital design
n3:klicoveSlovo
n14:fault%20tolerant%20design n14:hardware%20fault%20emulation n14:digital%20design
n3:kontrolniKodProRIV
[FABBBD7CF31A]
n3:mistoKonaniAkce
Krakow
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n17:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n13:2007
n3:tvurceVysledku
Kubátová, Hana Kubalík, Pavel Kvasnička, Jiří
n3:typAkce
n4:WRD
n3:zahajeniAkce
2007-04-10+02:00
n3:zamer
n9:MSM6840770014
s:numberOfPages
4
n21:hasPublisher
IEEE Computer Society
n11:isbn
1-4244-1161-0
n20:organizacniJednotka
21230