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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F07%3A03129811%21RIV08-GA0-21230___
rdf:type
skos:Concept n18:Vysledek
dcterms:description
Práce prezentuje návrh a výsledky aplikace metody pro zmenšení plochy křemíku zabraného IIR filtrem pomocí aplikace kvantizační zpětné vazby. A simple method to reduce the hardware cost (silicon area) of the biquadratic section implementation by means of error feedback (EF) is described. The optimization method utilizes the fact that the filter with an EF is more resistant to roundoff noise than a filter without it. An iterative method is used to reduce the occupied silicon area. Results show it is possible to spare up to 22\% of the occupied silicon area. Our findings are valid for FPGA as well as ASIC implementation of the IIR filters. Our method has an advantage in using a standard and already verified filtering IP core which results in design time reduction. A simple method to reduce the hardware cost (silicon area) of the biquadratic section implementation by means of error feedback (EF) is described. The optimization method utilizes the fact that the filter with an EF is more resistant to roundoff noise than a filter without it. An iterative method is used to reduce the occupied silicon area. Results show it is possible to spare up to 22\% of the occupied silicon area. Our findings are valid for FPGA as well as ASIC implementation of the IIR filters. Our method has an advantage in using a standard and already verified filtering IP core which results in design time reduction.
dcterms:title
Snížení plochy křemíku zabrané IIR filtrem pomocí kvantizační zpětné vazby Filter Hardware Cost Reduction by Means of Error Feedback Filter Hardware Cost Reduction by Means of Error Feedback
skos:prefLabel
Filter Hardware Cost Reduction by Means of Error Feedback Filter Hardware Cost Reduction by Means of Error Feedback Snížení plochy křemíku zabrané IIR filtrem pomocí kvantizační zpětné vazby
skos:notation
RIV/68407700:21230/07:03129811!RIV08-GA0-21230___
n3:strany
73;78
n3:aktivita
n11:P
n3:aktivity
P(GD102/03/H085)
n3:dodaniDat
n10:2008
n3:domaciTvurceVysledku
n4:3013472 n4:3925919
n3:druhVysledku
n21:D
n3:duvernostUdaju
n7:S
n3:entitaPredkladatele
n15:predkladatel
n3:idSjednocenehoVysledku
421938
n3:idVysledku
RIV/68407700:21230/07:03129811
n3:jazykVysledku
n19:eng
n3:klicovaSlova
ASIC design styles; FPGA design; IIR biquadratic section; digital filter implementation; error feedback
n3:klicoveSlovo
n6:IIR%20biquadratic%20section n6:ASIC%20design%20styles n6:digital%20filter%20implementation n6:FPGA%20design n6:error%20feedback
n3:kontrolniKodProRIV
[697FD638AC82]
n3:mistoKonaniAkce
VUT v Brně, FEKT, ÚREL
n3:mistoVydani
Piscataway
n3:nazevZdroje
Proceedings of 17th International Conference Radioelektronika 2007
n3:obor
n5:JA
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n12:GD102%2F03%2FH085
n3:rokUplatneniVysledku
n10:2007
n3:tvurceVysledku
Ručkay, Lukáš Šťastný, Jakub
n3:typAkce
n16:EUR
n3:zahajeniAkce
2007-04-24+02:00
s:numberOfPages
6
n14:hasPublisher
Institute of Electrical and Electronic Engineers
n17:isbn
1-4244-0821-0
n20:organizacniJednotka
21230