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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03121486%21RIV07-GA0-21230___
rdf:type
skos:Concept n20:Vysledek
dcterms:description
This paper deals with design methodology of high reliable digital system based on modified duplex system. Our modified duplex system is based on two FPGAs, where every FPGA can be reconfigured when a fault is detected. Design implemented in each FPGAs is based on one of several methods how to ensure the self checking properties. Our design methodology reflects requirements on area overhead and value of dependability parameters. Our modified duplex system is compared with standard duplex system. Our dependability model and dependability calculations are used to quantify proposed solutions. Availability parameters have been calculated by dependability Markov models. The final reliable system is fault tolerant. This paper deals with design methodology of high reliable digital system based on modified duplex system. Our modified duplex system is based on two FPGAs, where every FPGA can be reconfigured when a fault is detected. Design implemented in each FPGAs is based on one of several methods how to ensure the self checking properties. Our design methodology reflects requirements on area overhead and value of dependability parameters. Our modified duplex system is compared with standard duplex system. Our dependability model and dependability calculations are used to quantify proposed solutions. Availability parameters have been calculated by dependability Markov models. The final reliable system is fault tolerant. Není k dispozici
dcterms:title
Design Methodology for High Reliable System Design Methodology for High Reliable System Není k dispozici
skos:prefLabel
Design Methodology for High Reliable System Není k dispozici Design Methodology for High Reliable System
skos:notation
RIV/68407700:21230/06:03121486!RIV07-GA0-21230___
n3:strany
274 ; 279
n3:aktivita
n5:P n5:Z
n3:aktivity
P(GA102/04/0737), Z(MSM6840770014)
n3:dodaniDat
n10:2007
n3:domaciTvurceVysledku
n16:7205651 n16:7140827
n3:druhVysledku
n8:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n14:predkladatel
n3:idSjednocenehoVysledku
470920
n3:idVysledku
RIV/68407700:21230/06:03121486
n3:jazykVysledku
n12:eng
n3:klicovaSlova
TSC circuit, reliability, dependability, fault-tolerant, FPGA
n3:klicoveSlovo
n9:TSC%20circuit n9:FPGA n9:fault-tolerant n9:dependability n9:reliability
n3:kontrolniKodProRIV
[4AFE13736A2B]
n3:mistoKonaniAkce
Herl'any
n3:mistoVydani
Ko1ice
n3:nazevZdroje
Proceedings of the Seventh International Scientific Conference on Electronic Computers and Informatics ECI 2006
n3:obor
n19:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n4:GA102%2F04%2F0737
n3:rokUplatneniVysledku
n10:2006
n3:tvurceVysledku
Kubalík, Pavel Kubátová, Hana
n3:typAkce
n17:WRD
n3:zahajeniAkce
2006-09-20+02:00
n3:zamer
n22:MSM6840770014
s:numberOfPages
6
n13:hasPublisher
Technická univerzita v Košiciach
n21:isbn
80-8073-598-0
n15:organizacniJednotka
21230