This HTML5 document contains 50 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n18http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n22http://localhost/temp/predkladatel/
n11http://purl.org/net/nknouf/ns/bibtex#
n12http://linked.opendata.cz/resource/domain/vavai/projekt/
n7http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n20http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F68407700%3A21230%2F06%3A03121358%21RIV07-GA0-21230___/
n10http://linked.opendata.cz/ontology/domain/vavai/
n16https://schema.org/
n14http://linked.opendata.cz/resource/domain/vavai/zamer/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n4http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n13http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n15http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n6http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n19http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n21http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03121358%21RIV07-GA0-21230___
rdf:type
n10:Vysledek skos:Concept
dcterms:description
A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained by XILINX FPGA implementation by EDA tools. The dependability model and dependability calculations are presented. Není k dispozici A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained by XILINX FPGA implementation by EDA tools. The dependability model and dependability calculations are presented.
dcterms:title
Dependable Design for FPGA based on Duplex System and Reconfiguration Dependable Design for FPGA based on Duplex System and Reconfiguration Není k dispozici
skos:prefLabel
Dependable Design for FPGA based on Duplex System and Reconfiguration Není k dispozici Dependable Design for FPGA based on Duplex System and Reconfiguration
skos:notation
RIV/68407700:21230/06:03121358!RIV07-GA0-21230___
n3:strany
139 ; 145
n3:aktivita
n6:Z n6:P
n3:aktivity
P(GA102/04/2137), Z(MSM6840770014)
n3:dodaniDat
n21:2007
n3:domaciTvurceVysledku
n7:7205651 n7:7140827 n7:4622219
n3:druhVysledku
n19:D
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
470785
n3:idVysledku
RIV/68407700:21230/06:03121358
n3:jazykVysledku
n15:eng
n3:klicovaSlova
dependability, reconfiguration, FPGA, on-line testing
n3:klicoveSlovo
n4:FPGA n4:dependability n4:on-line%20testing n4:reconfiguration
n3:kontrolniKodProRIV
[2AF755291403]
n3:mistoKonaniAkce
Cavtat
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings of 9th Euromicro Conference on Digital System Design
n3:obor
n8:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n12:GA102%2F04%2F2137
n3:rokUplatneniVysledku
n21:2006
n3:tvurceVysledku
Dobiá1, Radek Kubátová, Hana Kubalík, Pavel
n3:typAkce
n18:WRD
n3:zahajeniAkce
2006-08-30+02:00
n3:zamer
n14:MSM6840770014
s:numberOfPages
7
n11:hasPublisher
IEEE Computer Society
n16:isbn
0-7695-2609-8
n22:organizacniJednotka
21230