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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03121303%21RIV07-GA0-21230___
rdf:type
n11:Vysledek skos:Concept
dcterms:description
Elánek popisuje metodologi ivytvooení vestaviného diagnostického systému do Soc obvodu. This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams. This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams.
dcterms:title
Samoeinné testování SoC obvodu s redukovanou potoebou pameti a minimalizovaným hardwarovym po3adavkem Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
skos:prefLabel
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead Samoeinné testování SoC obvodu s redukovanou potoebou pameti a minimalizovaným hardwarovym po3adavkem
skos:notation
RIV/68407700:21230/06:03121303!RIV07-GA0-21230___
n4:strany
300 ; 308
n4:aktivita
n5:P
n4:aktivity
P(1QS108040510), P(GA102/04/2137)
n4:dodaniDat
n12:2007
n4:domaciTvurceVysledku
n10:9570748
n4:druhVysledku
n19:D
n4:duvernostUdaju
n8:S
n4:entitaPredkladatele
n9:predkladatel
n4:idSjednocenehoVysledku
498808
n4:idVysledku
RIV/68407700:21230/06:03121303
n4:jazykVysledku
n20:eng
n4:klicovaSlova
Not available
n4:klicoveSlovo
n16:Not%20available
n4:kontrolniKodProRIV
[CA0C87BF52EC]
n4:mistoKonaniAkce
Arlington
n4:mistoVydani
Los Alamitos
n4:nazevZdroje
The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
n4:obor
n17:JC
n4:pocetDomacichTvurcuVysledku
1
n4:pocetTvurcuVysledku
5
n4:projekt
n6:1QS108040510 n6:GA102%2F04%2F2137
n4:rokUplatneniVysledku
n12:2006
n4:tvurceVysledku
Jarkovský, M. Novák, Ondřej Mader, Z. Jeníeek, J. Plíva, Z.
n4:typAkce
n21:WRD
n4:zahajeniAkce
2006-10-04+02:00
s:numberOfPages
9
n14:hasPublisher
IEEE Computer Society
n18:isbn
0-7695-2706-X
n7:organizacniJednotka
21230