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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03120136%21RIV07-GA0-21230___
rdf:type
n11:Vysledek skos:Concept
dcterms:description
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults. This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults. This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.
dcterms:title
Fault Tolerant System Design Method Based on Self-Checking Circuits Fault Tolerant System Design Method Based on Self-Checking Circuits Fault Tolerant System Design Method Based on Self-Checking Circuits
skos:prefLabel
Fault Tolerant System Design Method Based on Self-Checking Circuits Fault Tolerant System Design Method Based on Self-Checking Circuits Fault Tolerant System Design Method Based on Self-Checking Circuits
skos:notation
RIV/68407700:21230/06:03120136!RIV07-GA0-21230___
n3:strany
185 ; 186
n3:aktivita
n9:Z n9:P
n3:aktivity
P(GA102/04/0737), Z(MSM6840770014)
n3:dodaniDat
n5:2007
n3:domaciTvurceVysledku
n13:7140827 n13:7205651 n13:2194937
n3:druhVysledku
n18:D
n3:duvernostUdaju
n8:S
n3:entitaPredkladatele
n4:predkladatel
n3:idSjednocenehoVysledku
475636
n3:idVysledku
RIV/68407700:21230/06:03120136
n3:jazykVysledku
n19:eng
n3:klicovaSlova
FPGA, reconfiguration, fault tolerance, self-checking circuit
n3:klicoveSlovo
n16:fault%20tolerance n16:self-checking%20circuit n16:reconfiguration n16:FPGA
n3:kontrolniKodProRIV
[196F9C688A93]
n3:mistoKonaniAkce
Como
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium
n3:obor
n15:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n22:GA102%2F04%2F0737
n3:rokUplatneniVysledku
n5:2006
n3:tvurceVysledku
Fi1er, Petr Kubátová, Hana Kubalík, Pavel
n3:typAkce
n17:WRD
n3:zahajeniAkce
2006-07-10+02:00
n3:zamer
n21:MSM6840770014
s:numberOfPages
2
n14:hasPublisher
IEEE Computer Society
n12:isbn
0-7695-2620-9
n20:organizacniJednotka
21230