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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03120123%21RIV07-GA0-21230___
rdf:type
skos:Concept n12:Vysledek
dcterms:description
Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. The newly proposed enhancement consists in a major generalization of the method. The ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. The complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks. Není k dispozici Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. The newly proposed enhancement consists in a major generalization of the method. The ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. The complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks.
dcterms:title
Multiple-Vector Column-Matching BIST Design Method Není k dispozici Multiple-Vector Column-Matching BIST Design Method
skos:prefLabel
Multiple-Vector Column-Matching BIST Design Method Multiple-Vector Column-Matching BIST Design Method Není k dispozici
skos:notation
RIV/68407700:21230/06:03120123!RIV07-GA0-21230___
n3:strany
268 ; 273
n3:aktivita
n8:P n8:Z
n3:aktivity
P(GA102/04/2137), Z(MSM6840770014)
n3:dodaniDat
n14:2007
n3:domaciTvurceVysledku
n7:7140827 n7:2194937
n3:druhVysledku
n13:D
n3:duvernostUdaju
n21:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
487314
n3:idVysledku
RIV/68407700:21230/06:03120123
n3:jazykVysledku
n11:eng
n3:klicovaSlova
built-in self-test (BIST), ATPG, column-matching algorithm
n3:klicoveSlovo
n15:ATPG n15:column-matching%20algorithm n15:built-in%20self-test%20%28BIST%29
n3:kontrolniKodProRIV
[F097BC235597]
n3:mistoKonaniAkce
Praha
n3:mistoVydani
Praha
n3:nazevZdroje
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n22:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n6:GA102%2F04%2F2137
n3:rokUplatneniVysledku
n14:2006
n3:tvurceVysledku
Kubátová, Hana Fi1er, Petr
n3:typAkce
n16:EUR
n3:zahajeniAkce
2006-04-18+02:00
n3:zamer
n19:MSM6840770014
s:numberOfPages
6
n9:hasPublisher
Česká technika - nakladatelství ČVUT
n17:isbn
1-4244-0184-4
n10:organizacniJednotka
21230