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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03119432%21RIV07-GA0-21230___
rdf:type
skos:Concept n20:Vysledek
dcterms:description
Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %). Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %). Námi navr3ená zpitni-odvozující struktura generuje v1echny platné vstupní vektory k poilo3enému výstupnímu vektoru, vstupní vektor je generován bihem pouze jednoho hodinového cyklu, dvi varianty rekonfigurace pro zrychlení generování vektoru, experimentální data získána nad ISCAS'85. Vyu3ití rekonfigurace pro malé obvody není dostateeni efektivní (prumirná prostorová slo3itost je okolo 120 %, prumirné zrychlení je v1ak pouze okolo 9,3 %), ale pro velké obvody je poijatelný (prumirná prostorová slo3itost je okolo 96 %, prumirné zrychlení je okolo 21,5 %).
dcterms:title
Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process Rekonfigurace backtrace algoritmu implementovaného v HW pro zrychlení procesu generování vektoru
skos:prefLabel
Rekonfigurace backtrace algoritmu implementovaného v HW pro zrychlení procesu generování vektoru Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process
skos:notation
RIV/68407700:21230/06:03119432!RIV07-GA0-21230___
n4:strany
59 ; 64
n4:aktivita
n5:Z n5:P
n4:aktivity
P(GA102/04/2137), Z(MSM6840770014)
n4:dodaniDat
n16:2007
n4:domaciTvurceVysledku
n10:9192832 n10:9570748
n4:druhVysledku
n17:D
n4:duvernostUdaju
n8:S
n4:entitaPredkladatele
n21:predkladatel
n4:idSjednocenehoVysledku
496734
n4:idVysledku
RIV/68407700:21230/06:03119432
n4:jazykVysledku
n19:eng
n4:klicovaSlova
backtrace; hardware; reconfiguration; scan design; vector generation
n4:klicoveSlovo
n6:reconfiguration n6:backtrace n6:hardware n6:vector%20generation n6:scan%20design
n4:kontrolniKodProRIV
[FF7567632EF7]
n4:mistoKonaniAkce
Cluj-Napoca
n4:mistoVydani
Piscataway
n4:nazevZdroje
Proceedings of the 2006 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics
n4:obor
n11:IN
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:projekt
n22:GA102%2F04%2F2137
n4:rokUplatneniVysledku
n16:2006
n4:tvurceVysledku
Šťáva, Martin Novák, Ondřej
n4:typAkce
n18:WRD
n4:zahajeniAkce
2006-05-25+02:00
n4:zamer
n13:MSM6840770014
s:numberOfPages
6
n14:hasPublisher
IEEE
n15:isbn
1-4244-0360-X
n7:organizacniJednotka
21230