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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03119426%21RIV07-GA0-21230___
rdf:type
n7:Vysledek skos:Concept
dcterms:description
The backtrace models implemented in hardware and simulation of one of them are presented. These models perform input vector derivation of any combinational circuit part on the basis of the output vector knowledge and constraints. In this paper we introduce two different models serving as backtrace units. The behavioural models have been described in the language VHDL. Presentuje backtrace modely implementované v hardwaru a simulaci jednoho z nich. Oba tyto modely provádijí odvozování vstupního vektoru jakékoliv eásti kombinaeního obvodu na základi znalosti výstupního vektoru a omezujících podmínek. Jsou zde uvedeny dva odli1né modely slou3ící jako backtrace jednotky. Modely na úrovni popisu chování byly zapsány v jazyku VHDL. The backtrace models implemented in hardware and simulation of one of them are presented. These models perform input vector derivation of any combinational circuit part on the basis of the output vector knowledge and constraints. In this paper we introduce two different models serving as backtrace units. The behavioural models have been described in the language VHDL.
dcterms:title
A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation Model struktury pro odvozování vstupních vektoru kombinaeních obvodu a jeho simulace A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation
skos:prefLabel
A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation Model struktury pro odvozování vstupních vektoru kombinaeních obvodu a jeho simulace A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation
skos:notation
RIV/68407700:21230/06:03119426!RIV07-GA0-21230___
n3:strany
51 ; 57
n3:aktivita
n8:P n8:Z
n3:aktivity
P(GA102/04/2137), Z(MSM6840770014)
n3:dodaniDat
n4:2007
n3:domaciTvurceVysledku
n15:9192832 n15:9570748
n3:druhVysledku
n12:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n16:predkladatel
n3:idSjednocenehoVysledku
463847
n3:idVysledku
RIV/68407700:21230/06:03119426
n3:jazykVysledku
n11:eng
n3:klicovaSlova
backtrace; digital circuit; hardware; modelling; simulation
n3:klicoveSlovo
n9:hardware n9:modelling n9:digital%20circuit n9:simulation n9:backtrace
n3:kontrolniKodProRIV
[D2C69364102B]
n3:mistoKonaniAkce
Poerov
n3:mistoVydani
Ostrava
n3:nazevZdroje
Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems
n3:obor
n6:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n14:GA102%2F04%2F2137
n3:rokUplatneniVysledku
n4:2006
n3:tvurceVysledku
Novák, Ondřej Šťáva, Martin
n3:typAkce
n17:EUR
n3:zahajeniAkce
2006-04-25+02:00
n3:zamer
n21:MSM6840770014
s:numberOfPages
7
n22:hasPublisher
MARQ
n10:isbn
80-86840-21-2
n20:organizacniJednotka
21230