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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A03119425%21RIV07-GA0-21230___
rdf:type
n15:Vysledek skos:Concept
dcterms:description
This paper presents simulation of the proposed architecture for backward determination of input vectors by HW. An example of a simple combinational circuit and a corresponding backward-determining circuit is completely analysed there. A simulation process of this example for some output vectors is stated as well. At the end of the paper, there are calculated three indicators showing the quality of the backtrace algorithm implemented in HW. This paper presents simulation of the proposed architecture for backward determination of input vectors by HW. An example of a simple combinational circuit and a corresponding backward-determining circuit is completely analysed there. A simulation process of this example for some output vectors is stated as well. At the end of the paper, there are calculated three indicators showing the quality of the backtrace algorithm implemented in HW. Elánek presentuje simulaci navr3ené architektury pro zpitné odvozování vstupních vektoru pomocí HW. Je zde proveden rozbor poíkladu jednoduchého kombinaeního obvodu a odpovídajícího zpitni-odvozujícího obvodu. Simulaení proces tohoto poíkladu pro nikolik výstupních vektoru je rovni3 uveden. Dále jsou vypoeteny toi ukazatele ureující kvalitu backtrace algoritmu implementovaného v HW.
dcterms:title
An Illustrative Case Study of Backward Determination of Input Vectors by HW Ilustrativní poípadová studie zpitného odvozování vstupních vektoru pomocí HW An Illustrative Case Study of Backward Determination of Input Vectors by HW
skos:prefLabel
An Illustrative Case Study of Backward Determination of Input Vectors by HW An Illustrative Case Study of Backward Determination of Input Vectors by HW Ilustrativní poípadová studie zpitného odvozování vstupních vektoru pomocí HW
skos:notation
RIV/68407700:21230/06:03119425!RIV07-GA0-21230___
n5:strany
253 ; 258
n5:aktivita
n13:Z n13:P
n5:aktivity
P(GA102/04/2137), Z(MSM6840770014)
n5:dodaniDat
n14:2007
n5:domaciTvurceVysledku
n6:9570748 n6:9192832
n5:druhVysledku
n18:D
n5:duvernostUdaju
n8:S
n5:entitaPredkladatele
n21:predkladatel
n5:idSjednocenehoVysledku
464809
n5:idVysledku
RIV/68407700:21230/06:03119425
n5:jazykVysledku
n16:eng
n5:klicovaSlova
backtrace; backward determination; digital circuit; hardware; simulation; vectors generation
n5:klicoveSlovo
n7:hardware n7:vectors%20generation n7:digital%20circuit n7:backward%20determination n7:backtrace n7:simulation
n5:kontrolniKodProRIV
[16896EF89FB3]
n5:mistoKonaniAkce
Poerov
n5:mistoVydani
Ostrava
n5:nazevZdroje
Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems
n5:obor
n12:IN
n5:pocetDomacichTvurcuVysledku
2
n5:pocetTvurcuVysledku
2
n5:projekt
n20:GA102%2F04%2F2137
n5:rokUplatneniVysledku
n14:2006
n5:tvurceVysledku
Novák, Ondřej Šťáva, Martin
n5:typAkce
n22:EUR
n5:zahajeniAkce
2006-04-25+02:00
n5:zamer
n19:MSM6840770014
s:numberOfPages
6
n11:hasPublisher
MARQ
n9:isbn
80-86840-21-2
n4:organizacniJednotka
21230