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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A00126094%21RIV11-MSM-21230___
rdf:type
n11:Vysledek skos:Concept
dcterms:description
In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors into two dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification. Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL. In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors into two dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification. Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL.
dcterms:title
An Accelerator for Kohonen Self-Organizing Maps An Accelerator for Kohonen Self-Organizing Maps
skos:prefLabel
An Accelerator for Kohonen Self-Organizing Maps An Accelerator for Kohonen Self-Organizing Maps
skos:notation
RIV/68407700:21230/06:00126094!RIV11-MSM-21230___
n3:aktivita
n20:Z
n3:aktivity
Z(MSM6840770012)
n3:dodaniDat
n6:2011
n3:domaciTvurceVysledku
n9:4691016 n9:2715279 n9:3013472
n3:druhVysledku
n10:D
n3:duvernostUdaju
n16:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
464741
n3:idVysledku
RIV/68407700:21230/06:00126094
n3:jazykVysledku
n13:eng
n3:klicovaSlova
ANN; FPGA; KSOM; accelerator; self-organizing maps; speech
n3:klicoveSlovo
n4:ANN n4:KSOM n4:accelerator n4:self-organizing%20maps n4:speech n4:FPGA
n3:kontrolniKodProRIV
[DF9BBD1B521C]
n3:mistoKonaniAkce
Žilina
n3:mistoVydani
Žilina
n3:nazevZdroje
Digital Technologies 2006 - 3rd International Workshop
n3:obor
n8:JA
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n6:2006
n3:tvurceVysledku
Bártů, Marek Šťastný, Jakub Tučková, Jana
n3:typAkce
n15:WRD
n3:zahajeniAkce
2006-12-01+01:00
n3:zamer
n17:MSM6840770012
s:numberOfPages
6
n12:hasPublisher
Žilinská univerzita v Žiline. Elektrotechnická fakulta
n5:isbn
80-8070-637-9
n21:organizacniJednotka
21230