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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F06%3A00120468%21RIV12-GA0-21230___
rdf:type
skos:Concept n15:Vysledek
dcterms:description
Fault simulation allows evaluation of reliability properties of developed designs. The complexity of the designs is growing, which makes software-based simulation methods unusable. Hardware-based fault simulation can bring desired speedup. Partial dynamic reconfiguration is a one way of fault injection. This paper describes a simulator based on this technique and shows that partial dynamic reconfiguration is an effective way of fault injection. Error-detection code based CED circuits are used in experiments; the results of the experiments are reported. Fault simulation allows evaluation of reliability properties of developed designs. The complexity of the designs is growing, which makes software-based simulation methods unusable. Hardware-based fault simulation can bring desired speedup. Partial dynamic reconfiguration is a one way of fault injection. This paper describes a simulator based on this technique and shows that partial dynamic reconfiguration is an effective way of fault injection. Error-detection code based CED circuits are used in experiments; the results of the experiments are reported.
dcterms:title
FPGA-based Fault Simulator FPGA-based Fault Simulator
skos:prefLabel
FPGA-based Fault Simulator FPGA-based Fault Simulator
skos:notation
RIV/68407700:21230/06:00120468!RIV12-GA0-21230___
n3:aktivita
n6:P n6:Z
n3:aktivity
P(1QS108040510), P(GA102/04/2137), Z(AV0Z10750506)
n3:dodaniDat
n8:2012
n3:domaciTvurceVysledku
n19:2026449 n19:9570748
n3:druhVysledku
n22:D
n3:duvernostUdaju
n12:S
n3:entitaPredkladatele
n10:predkladatel
n3:idSjednocenehoVysledku
476260
n3:idVysledku
RIV/68407700:21230/06:00120468
n3:jazykVysledku
n17:eng
n3:klicovaSlova
FPGA; fault simulation
n3:klicoveSlovo
n16:FPGA n16:fault%20simulation
n3:kontrolniKodProRIV
[B6403F62C1D2]
n3:mistoKonaniAkce
Praha
n3:mistoVydani
Praha
n3:nazevZdroje
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n21:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n4:GA102%2F04%2F2137 n4:1QS108040510
n3:rokUplatneniVysledku
n8:2006
n3:tvurceVysledku
Novák, Ondřej Kafka, Leoš
n3:typAkce
n18:EUR
n3:wos
000238973400071
n3:zahajeniAkce
2006-04-18+02:00
n3:zamer
n11:AV0Z10750506
s:numberOfPages
5
n14:hasPublisher
Česká technika - nakladatelství ČVUT
n20:isbn
1-4244-0184-4
n13:organizacniJednotka
21230