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Statements

Subject Item

n2:RIV%2F68407700%3A21230%2F06%3A00117922%21RIV11-GA0-21230___

rdf:type

n17:Vysledek skos:Concept

dcterms:description

The backtrace algorithm for determination of input vectors of combinational circuits on the basis of output vector knowledge and other constraints implemented in an FPGA. Results are carried out for the ISCAS'85 benchmarks. The backtrace algorithm for determination of input vectors of combinational circuits on the basis of output vector knowledge and other constraints implemented in an FPGA. Results are carried out for the ISCAS'85 benchmarks.

dcterms:title

Implementation of the Backtrace Algorithm in an FPGA Implementation of the Backtrace Algorithm in an FPGA

skos:prefLabel

Implementation of the Backtrace Algorithm in an FPGA Implementation of the Backtrace Algorithm in an FPGA

skos:notation

RIV/68407700:21230/06:00117922!RIV11-GA0-21230___

n4:aktivita

n13:P

n4:aktivity

P(GA102/04/2137)

n4:dodaniDat

n12:2011

n4:domaciTvurceVysledku

n5:9570748 n5:9192832

n4:druhVysledku

n16:D

n4:duvernostUdaju

n7:S

n4:entitaPredkladatele

n9:predkladatel

n4:idSjednocenehoVysledku

479019

n4:idVysledku

RIV/68407700:21230/06:00117922

n4:jazykVysledku

n15:eng

n4:klicovaSlova

FPGA; backtrace; design-for-testability; test

n4:klicoveSlovo

n6:test n6:FPGA n6:backtrace n6:design-for-testability

n4:kontrolniKodProRIV

[38E1627C19EF]

n4:mistoKonaniAkce

Praha

n4:mistoVydani

Praha

n4:nazevZdroje

Proceedings of Workshop 2006

n4:obor

n18:JC

n4:pocetDomacichTvurcuVysledku

2

n4:pocetTvurcuVysledku

2

n4:projekt

n19:GA102%2F04%2F2137

n4:rokUplatneniVysledku

n12:2006

n4:tvurceVysledku

Novák, Ondřej Šťáva, Martin

n4:typAkce

n20:EUR

n4:zahajeniAkce

2006-02-20+01:00

s:numberOfPages

2

n11:hasPublisher

České vysoké učení technické v Praze

n14:isbn

80-01-03439-9

n21:organizacniJednotka

21230