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Statements

Subject Item

n2:RIV%2F68407700%3A21230%2F05%3A03117292%21RIV06-MSM-21230___

rdf:type

skos:Concept n17:Vysledek

dcterms:description

This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented. This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented. This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented.

dcterms:title

Parity Codes Used for On-line Testing in FPGA Parity Codes Used for On-line Testing in FPGA Parity Codes Used for On-line Testing in FPGA

skos:prefLabel

Parity Codes Used for On-line Testing in FPGA Parity Codes Used for On-line Testing in FPGA Parity Codes Used for On-line Testing in FPGA

skos:notation

RIV/68407700:21230/05:03117292!RIV06-MSM-21230___

n3:strany

53 ; 59

n3:aktivita

n14:Z

n3:aktivity

Z(MSM6840770014)

n3:cisloPeriodika

6

n3:dodaniDat

n4:2006

n3:domaciTvurceVysledku

n10:7140827 n10:7205651

n3:druhVysledku

n8:J

n3:duvernostUdaju

n18:S

n3:entitaPredkladatele

n15:predkladatel

n3:idSjednocenehoVysledku

535439

n3:idVysledku

RIV/68407700:21230/05:03117292

n3:jazykVysledku

n11:eng

n3:klicovaSlova

On-line testing, self-checking, error detection code, fault, error, FPGA

n3:klicoveSlovo

n6:fault n6:error%20detection%20code n6:On-line%20testing n6:error n6:FPGA n6:self-checking

n3:kodStatuVydavatele

CZ - Česká republika

n3:kontrolniKodProRIV

[6DF0B0D7A410]

n3:nazevZdroje

Acta Polytechnica

n3:obor

n13:JC

n3:pocetDomacichTvurcuVysledku

2

n3:pocetTvurcuVysledku

2

n3:rokUplatneniVysledku

n4:2005

n3:svazekPeriodika

45

n3:tvurceVysledku

Kubátová, Hana Kubalík, Pavel

n3:zamer

n16:MSM6840770014

s:issn

1210-2709

s:numberOfPages

7

n12:organizacniJednotka

21230