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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F05%3A03111857%21RIV06-MSM-21230___
rdf:type
n13:Vysledek skos:Concept
dcterms:description
This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. The implementation data for two dynamically reconfigurable platforms available on the market - the Xilinx Virtex2 family FPGAs and the Atmel FPSLIC family FPGAs - is compared in terms of resource requirements, operating frequency, and power consumption. Není k dispozici Není k dispozici
dcterms:title
Dynamic Reconfiguration in FPGA-based Designs Dynamic Reconfiguration in FPGA-based Designs Dynamic Reconfiguration in FPGA-based Designs
skos:prefLabel
Dynamic Reconfiguration in FPGA-based Designs Dynamic Reconfiguration in FPGA-based Designs Dynamic Reconfiguration in FPGA-based Designs
skos:notation
RIV/68407700:21230/05:03111857!RIV06-MSM-21230___
n3:strany
129 ; 136
n3:aktivita
n6:P
n3:aktivity
P(1M0567)
n3:dodaniDat
n12:2006
n3:domaciTvurceVysledku
n7:4726731 n7:6719791
n3:druhVysledku
n14:D
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n17:predkladatel
n3:idSjednocenehoVysledku
518925
n3:idVysledku
RIV/68407700:21230/05:03111857
n3:jazykVysledku
n16:cze
n3:klicovaSlova
Dynamic Reconfiguration; FPGA
n3:klicoveSlovo
n9:FPGA n9:Dynamic%20Reconfiguration
n3:kontrolniKodProRIV
[19CF8F1A29EA]
n3:mistoKonaniAkce
Sopron
n3:mistoVydani
Sopron
n3:nazevZdroje
Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
n3:obor
n10:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
4
n3:projekt
n4:1M0567
n3:rokUplatneniVysledku
n12:2005
n3:tvurceVysledku
Bartosinski, Roman Honzík, Petr Daněk, M. Matoušek, R.
n3:typAkce
n18:WRD
n3:zahajeniAkce
2005-04-13+02:00
s:numberOfPages
8
n19:hasPublisher
University of Western Hungary
n15:isbn
963-9364-48-7
n21:organizacniJednotka
21230