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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F05%3A03109967%21RIV06-GA0-21230___
rdf:type
n12:Vysledek skos:Concept
dcterms:description
Článek se zabýva návrhem vysoce spolehlivých obvod implementovaných pomocí FPGA obvodů. Návrh je založen na jednoduchém zdvojení obvodů splňujících podminky pro návrh TSC obvodu. This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools. This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools.
dcterms:title
Vysoce spolehlivý návrh TSC obvodů Highly Reliable Design Based on TSC Circuits Highly Reliable Design Based on TSC Circuits
skos:prefLabel
Highly Reliable Design Based on TSC Circuits Vysoce spolehlivý návrh TSC obvodů Highly Reliable Design Based on TSC Circuits
skos:notation
RIV/68407700:21230/05:03109967!RIV06-GA0-21230___
n3:strany
101 ; 106
n3:aktivita
n8:P n8:Z
n3:aktivity
P(GA102/03/0672), Z(MSM6840770014)
n3:dodaniDat
n16:2006
n3:domaciTvurceVysledku
n5:7205651 n5:7140827
n3:druhVysledku
n10:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
523314
n3:idVysledku
RIV/68407700:21230/05:03109967
n3:jazykVysledku
n14:eng
n3:klicovaSlova
FPGA, tottaly self-checking (TSC) circuit, dependability, concurrent error detection (CED)
n3:klicoveSlovo
n15:concurrent%20error%20detection%20%28CED%29 n15:tottaly%20self-checking%20%28TSC%29%20circuit n15:dependability n15:FPGA
n3:kontrolniKodProRIV
[10459FE9436E]
n3:mistoKonaniAkce
Lázně Sedmihorky
n3:mistoVydani
Praha
n3:nazevZdroje
Počítačové architektury & diagnostika
n3:obor
n6:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n13:GA102%2F03%2F0672
n3:rokUplatneniVysledku
n16:2005
n3:tvurceVysledku
Kubátová, Hana Kubalík, Pavel
n3:typAkce
n17:EUR
n3:zahajeniAkce
2005-09-21+02:00
n3:zamer
n21:MSM6840770014
s:numberOfPages
6
n19:hasPublisher
České vysoké učení technické v Praze. Fakulta elektrotechnická. Katedra počítačů
n22:isbn
80-01-03298-1
n9:organizacniJednotka
21230