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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F05%3A03108032%21RIV06-GA0-21230___
rdf:type
n11:Vysledek skos:Concept
dcterms:description
Není k dispozici This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered. This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered.
dcterms:title
Fault Classification for Self-checking Circuits Implemented in FPGA Není k dispozici Fault Classification for Self-checking Circuits Implemented in FPGA
skos:prefLabel
Fault Classification for Self-checking Circuits Implemented in FPGA Není k dispozici Fault Classification for Self-checking Circuits Implemented in FPGA
skos:notation
RIV/68407700:21230/05:03108032!RIV06-GA0-21230___
n3:strany
228 ; 231
n3:aktivita
n12:Z n12:P
n3:aktivity
P(GA102/04/2137), Z(MSM6840770014)
n3:dodaniDat
n21:2006
n3:domaciTvurceVysledku
n7:7140827 n7:9570748 n7:2026449 n7:7205651
n3:druhVysledku
n19:D
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
521445
n3:idVysledku
RIV/68407700:21230/05:03108032
n3:jazykVysledku
n4:eng
n3:klicovaSlova
fault security, self-testing, fault tolerant,, digital design. testing, FPGA
n3:klicoveSlovo
n5:fault%20security n5:fault%20tolerant n5:digital%20design.%20testing n5:FPGA n5:self-testing
n3:kontrolniKodProRIV
[D7866F3DC291]
n3:mistoKonaniAkce
Sopron
n3:mistoVydani
Sopron
n3:nazevZdroje
Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
n3:obor
n8:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n6:GA102%2F04%2F2137
n3:rokUplatneniVysledku
n21:2005
n3:tvurceVysledku
Kubátová, Hana Novák, Ondřej Kubalík, Pavel Kafka, Leoš
n3:typAkce
n22:WRD
n3:zahajeniAkce
2005-04-13+02:00
n3:zamer
n15:MSM6840770014
s:numberOfPages
4
n16:hasPublisher
University of Western Hungary
n20:isbn
963-9364-48-7
n17:organizacniJednotka
21230