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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F04%3A03107162%21RIV%2F2005%2FGA0%2F212305%2FN
rdf:type
n11:Vysledek skos:Concept
dcterms:description
Není k dispozici This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation. Due to their further implementation in FPGAs the fault model considers that the configuration data are stored in the configuration memory. This work is a part of a more complex methodology of a fault tolerant design based on FPGAs with dynamical reconfiguration of the faulty part of the designed circuit. This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation. Due to their further implementation in FPGAs the fault model considers that the configuration data are stored in the configuration memory. This work is a part of a more complex methodology of a fault tolerant design based on FPGAs with dynamical reconfiguration of the faulty part of the designed circuit.
dcterms:title
Fault Tolerant Design Methodology Není k dispozici Fault Tolerant Design Methodology
skos:prefLabel
Fault Tolerant Design Methodology Fault Tolerant Design Methodology Není k dispozici
skos:notation
RIV/68407700:21230/04:03107162!RIV/2005/GA0/212305/N
n3:aktivita
n4:P n4:Z
n3:aktivity
P(GA102/04/2137), Z(MSM 212300014)
n3:dodaniDat
n13:2005
n3:domaciTvurceVysledku
n12:7205651
n3:druhVysledku
n8:A
n3:duvernostUdaju
n14:S
n3:entitaPredkladatele
n15:predkladatel
n3:idSjednocenehoVysledku
564217
n3:idVysledku
RIV/68407700:21230/04:03107162
n3:jazykVysledku
n5:eng
n3:klicovaSlova
FPGA, on-line testing, fault-tolerance, error detection codes
n3:klicoveSlovo
n10:on-line%20testing n10:error%20detection%20codes n10:FPGA n10:fault-tolerance
n3:kodPristupu
n19:L
n3:kontrolniKodProRIV
[B578399FEBD9]
n3:mistoVydani
Praha
n3:nosic
neuvedeno
n3:obor
n16:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
1
n3:projekt
n17:GA102%2F04%2F2137
n3:rokUplatneniVysledku
n13:2004
n3:tvurceVysledku
Kubalík, Pavel
n3:zamer
n9:MSM%20212300014
n18:organizacniJednotka
21230