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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F04%3A03099879%21RIV%2F2005%2FGA0%2F212305%2FN
rdf:type
skos:Concept n13:Vysledek
dcterms:description
Není k dispozici The paper focuses on the minimization of the area overhead of check bits generator in the online BIST for circuits implemented in FPGAs. We have used error detection codes (ED codes) to ensure the self-checking property. The newly proposed simplification method consists of converting the duplicate circuit into a two-level network, for which the check-bits are generated. Then the outputs of the circuit are reduced to these check-bits only; the original outputs can be omitted. After that, a multi-level network is synthesized for this circuit. This notion enables us to significantly reduce the resulting logic. The paper focuses on the minimization of the area overhead of check bits generator in the online BIST for circuits implemented in FPGAs. We have used error detection codes (ED codes) to ensure the self-checking property. The newly proposed simplification method consists of converting the duplicate circuit into a two-level network, for which the check-bits are generated. Then the outputs of the circuit are reduced to these check-bits only; the original outputs can be omitted. After that, a multi-level network is synthesized for this circuit. This notion enables us to significantly reduce the resulting logic.
dcterms:title
Minimization of the Hamming Code Generator in Self Checking Circuits Není k dispozici Minimization of the Hamming Code Generator in Self Checking Circuits
skos:prefLabel
Minimization of the Hamming Code Generator in Self Checking Circuits Není k dispozici Minimization of the Hamming Code Generator in Self Checking Circuits
skos:notation
RIV/68407700:21230/04:03099879!RIV/2005/GA0/212305/N
n3:strany
161 ; 166
n3:aktivita
n7:P n7:Z
n3:aktivity
P(GA102/04/2137), Z(MSM 212300014)
n3:dodaniDat
n15:2005
n3:domaciTvurceVysledku
n11:2194937 n11:7140827 n11:7205651
n3:druhVysledku
n21:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n10:predkladatel
n3:idSjednocenehoVysledku
573726
n3:idVysledku
RIV/68407700:21230/04:03099879
n3:jazykVysledku
n22:eng
n3:klicovaSlova
FPGA, Built-In Self-Test (BIST), on-line, error detecting codes, self-checking circuit, totally self
n3:klicoveSlovo
n9:FPGA n9:on-line n9:self-checking%20circuit n9:error%20detecting%20codes n9:Built-In%20Self-Test%20%28BIST%29 n9:totally%20self
n3:kontrolniKodProRIV
[0452A1AE8517]
n3:mistoKonaniAkce
Dychow
n3:mistoVydani
Zielona Gora
n3:nazevZdroje
Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04
n3:obor
n4:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n14:GA102%2F04%2F2137
n3:rokUplatneniVysledku
n15:2004
n3:tvurceVysledku
Fišer, Petr Kubalík, Pavel Kubátová, Hana
n3:typAkce
n20:WRD
n3:zahajeniAkce
2004-09-15+02:00
n3:zamer
n19:MSM%20212300014
s:numberOfPages
6
n8:hasPublisher
University of Zielona Gora
n17:isbn
83-89712-15-6
n6:organizacniJednotka
21230