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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F03%3A03092667%21RIV%2F2004%2FGA0%2F212304%2FN
rdf:type
n11:Vysledek skos:Concept
dcterms:description
The paper focuses on error detection in circuits implemented in FPGAs using error detection codes(ED codes). The paper focuses on error detection in circuits implemented in FPGAs using error detection codes(ED codes).
dcterms:title
Design of Self Checking Circuits Based on FPGA Design of Self Checking Circuits Based on FPGA
skos:prefLabel
Design of Self Checking Circuits Based on FPGA Design of Self Checking Circuits Based on FPGA
skos:notation
RIV/68407700:21230/03:03092667!RIV/2004/GA0/212304/N
n4:strany
378 ; 381
n4:aktivita
n9:P n9:Z
n4:aktivity
P(GA102/03/0672), Z(MSM 212300014)
n4:dodaniDat
n5:2004
n4:domaciTvurceVysledku
n14:7140827 n14:7205651
n4:druhVysledku
n21:D
n4:duvernostUdaju
n17:S
n4:entitaPredkladatele
n10:predkladatel
n4:idSjednocenehoVysledku
603221
n4:idVysledku
RIV/68407700:21230/03:03092667
n4:jazykVysledku
n19:eng
n4:klicovaSlova
FPGA;error detection;on-line;self checking
n4:klicoveSlovo
n7:on-line n7:FPGA n7:error%20detection n7:self%20checking
n4:kontrolniKodProRIV
[60EE14F5216C]
n4:mistoKonaniAkce
Cairo
n4:mistoVydani
Cairo
n4:nazevZdroje
Proceedings of the 15th International Conference on Microelectronics
n4:obor
n18:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:projekt
n15:GA102%2F03%2F0672
n4:rokUplatneniVysledku
n5:2003
n4:tvurceVysledku
Kubalík, Pavel Kubátová, Hana
n4:typAkce
n22:WRD
n4:zahajeniAkce
2003-12-09+01:00
n4:zamer
n20:MSM%20212300014
s:numberOfPages
4
n6:hasPublisher
Cairo University
n12:isbn
977-05-2010-1
n16:organizacniJednotka
21230