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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F02%3A03074985%21RIV%2F2003%2FMSM%2F212303%2FN
rdf:type
n13:Vysledek skos:Concept
dcterms:description
Not available Not available
dcterms:title
Integrated Timing-Driven Approach to the FPGA Layout Integrated Timing-Driven Approach to the FPGA Layout
skos:prefLabel
Integrated Timing-Driven Approach to the FPGA Layout Integrated Timing-Driven Approach to the FPGA Layout
skos:notation
RIV/68407700:21230/02:03074985!RIV/2003/MSM/212303/N
n3:strany
693;696
n3:aktivita
n21:Z
n3:aktivity
Z(MSM 212300014)
n3:dodaniDat
n4:2003
n3:domaciTvurceVysledku
n10:4270320
n3:druhVysledku
n9:D
n3:duvernostUdaju
n17:S
n3:entitaPredkladatele
n11:predkladatel
n3:idSjednocenehoVysledku
649316
n3:idVysledku
RIV/68407700:21230/02:03074985
n3:jazykVysledku
n8:eng
n3:klicovaSlova
FPGA; integrated approach; physical design algorithms; placement; routing
n3:klicoveSlovo
n14:placement n14:physical%20design%20algorithms n14:integrated%20approach n14:FPGA n14:routing
n3:kontrolniKodProRIV
[4EB75D21DCB8]
n3:mistoKonaniAkce
Dubrovnik
n3:mistoVydani
Piscataway
n3:nazevZdroje
The 9th IEEE International Conference on Electronics, Circuits and Systems
n3:obor
n20:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:pocetUcastnikuAkce
0
n3:pocetZahranicnichUcastnikuAkce
0
n3:rokUplatneniVysledku
n4:2002
n3:tvurceVysledku
Daněk, Martin
n3:typAkce
n5:WRD
n3:zahajeniAkce
2002-09-15+02:00
n3:zamer
n12:MSM%20212300014
s:numberOfPages
4
n15:hasPublisher
IEEE
n18:isbn
0-7803-7596-3
n16:organizacniJednotka
21230