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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F02%3A03074683%21RIV%2F2003%2FMSM%2F212303%2FN
rdf:type
skos:Concept n14:Vysledek
dcterms:description
FPGA, physical design, placement, routing, delay estimation FPGA, physical design, placement, routing, delay estimation
dcterms:title
Integrated Iterative Approach to FPGA Placement Integrated Iterative Approach to FPGA Placement
skos:prefLabel
Integrated Iterative Approach to FPGA Placement Integrated Iterative Approach to FPGA Placement
skos:notation
RIV/68407700:21230/02:03074683!RIV/2003/MSM/212303/N
n3:strany
253;262
n3:aktivita
n16:Z
n3:aktivity
Z(MSM 212300014)
n3:dodaniDat
n4:2003
n3:domaciTvurceVysledku
n8:4270320
n3:druhVysledku
n13:D
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
649313
n3:idVysledku
RIV/68407700:21230/02:03074683
n3:jazykVysledku
n12:eng
n3:klicovaSlova
FPGA; delay estimation; physical design; placement; routing
n3:klicoveSlovo
n5:FPGA n5:routing n5:physical%20design n5:placement n5:delay%20estimation
n3:kontrolniKodProRIV
[2B6D85BE1334]
n3:mistoKonaniAkce
Montpellier
n3:mistoVydani
Berlin
n3:nazevZdroje
Field-Programmable Logic and Applications - FPL2002
n3:obor
n17:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:pocetUcastnikuAkce
0
n3:pocetZahranicnichUcastnikuAkce
0
n3:rokUplatneniVysledku
n4:2002
n3:tvurceVysledku
Daněk, Martin
n3:typAkce
n10:WRD
n3:zahajeniAkce
2002-09-02+02:00
n3:zamer
n11:MSM%20212300014
s:numberOfPages
10
n21:hasPublisher
Springer-Verlag
n6:isbn
3-540-44108-5
n19:organizacniJednotka
21230