This HTML5 document contains 40 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n16http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n17http://purl.org/net/nknouf/ns/bibtex#
n15http://localhost/temp/predkladatel/
n21http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n19http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F68407700%3A21230%2F02%3A03073747%21RIV%2F2003%2FMSM%2F212303%2FN/
n5http://linked.opendata.cz/ontology/domain/vavai/
n18http://linked.opendata.cz/resource/domain/vavai/zamer/
n11https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n6http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n10http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n12http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n4http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F02%3A03073747%21RIV%2F2003%2FMSM%2F212303%2FN
rdf:type
n5:Vysledek skos:Concept
dcterms:description
Delay estimation, physical design, FPGA, classifier systems, adaptive algorithms Delay estimation, physical design, FPGA, classifier systems, adaptive algorithms
dcterms:title
Reaching Optimal Performance of Timing-Driven Design Algorithms for FPGAs Reaching Optimal Performance of Timing-Driven Design Algorithms for FPGAs
skos:prefLabel
Reaching Optimal Performance of Timing-Driven Design Algorithms for FPGAs Reaching Optimal Performance of Timing-Driven Design Algorithms for FPGAs
skos:notation
RIV/68407700:21230/02:03073747!RIV/2003/MSM/212303/N
n3:strany
106;113
n3:aktivita
n8:Z
n3:aktivity
Z(MSM 212300014)
n3:dodaniDat
n4:2003
n3:domaciTvurceVysledku
n21:4270320
n3:druhVysledku
n12:D
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n19:predkladatel
n3:idSjednocenehoVysledku
661529
n3:idVysledku
RIV/68407700:21230/02:03073747
n3:jazykVysledku
n10:eng
n3:klicovaSlova
Not available
n3:klicoveSlovo
n6:Not%20available
n3:kontrolniKodProRIV
[C6374194BD04]
n3:mistoKonaniAkce
Brno
n3:mistoVydani
Brno
n3:nazevZdroje
Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002
n3:obor
n9:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
1
n3:pocetUcastnikuAkce
0
n3:pocetZahranicnichUcastnikuAkce
0
n3:rokUplatneniVysledku
n4:2002
n3:tvurceVysledku
Daněk, Martin
n3:typAkce
n16:EUR
n3:zahajeniAkce
2002-04-17+02:00
n3:zamer
n18:MSM%20212300014
s:numberOfPages
8
n17:hasPublisher
Vysoké učení technické v Brně
n11:isbn
80-214-2094-4
n15:organizacniJednotka
21230