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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F14%3A00438631%21RIV15-MSM-67985556
rdf:type
skos:Concept n20:Vysledek
rdfs:seeAlso
http://sp.utia.cz/index.php?ids=results&id=Utia_EdkDSP_Vivado_2013_4_KC705
dcterms:description
This application note describes the precompiled Vivado 2013.4 Kintex7 designs with the floating point EdkDSP accelerators and examples of use of basic communication and computation blocks used in the video processing and image processing applications. The MicroBlaze SoC design with the AXI bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Kintex7 KC705 board and the Vivado 2014.3 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP library described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 8 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx KC705 board with the 28nm Kintex7 xc7k325t-2 FPGA part. This application note describes the precompiled Vivado 2013.4 Kintex7 designs with the floating point EdkDSP accelerators and examples of use of basic communication and computation blocks used in the video processing and image processing applications. The MicroBlaze SoC design with the AXI bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Kintex7 KC705 board and the Vivado 2014.3 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP library described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 8 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx KC705 board with the 28nm Kintex7 xc7k325t-2 FPGA part.
dcterms:title
Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos
skos:prefLabel
Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos
skos:notation
RIV/67985556:_____/14:00438631!RIV15-MSM-67985556
n4:aktivita
n19:P
n4:aktivity
P(7H14004)
n4:dodaniDat
n17:2015
n4:domaciTvurceVysledku
n14:6386784
n4:druhVysledku
n13:G%2FB
n4:duvernostUdaju
n11:S
n4:ekonomickeParametry
Ověření 1 G ethernetu, file systemu, TFTP a WWW serveru v kombinaci s platformou EdkDSP pro výpočty v plovoucí řádové čárce na prototypové desce KC705.
n4:entitaPredkladatele
n6:predkladatel
n4:idSjednocenehoVysledku
8452
n4:idVysledku
RIV/67985556:_____/14:00438631
n4:interniIdentifikace
Utia_EdkDSP_Vivado_2013_4_KC705
n4:jazykVysledku
n8:eng
n4:kategorie
n10:A
n4:klicovaSlova
floating-point accelerator; programmable hardware; signal processing acceleration
n4:klicoveSlovo
n15:programmable%20hardware n15:signal%20processing%20acceleration n15:floating-point%20accelerator
n4:kontrolniKodProRIV
[FE486E8EBD6C]
n4:licencniPoplatek
n5:N
n4:obor
n18:JC
n4:pocetDomacichTvurcuVysledku
1
n4:pocetTvurcuVysledku
1
n4:projekt
n16:7H14004
n4:rokUplatneniVysledku
n17:2014
n4:technickeParametry
Demonstrátor dovolující připojení k 1G ethernet, generování www stránek a přenos souborů a použití akcelerátorů výpočtu v plovoucí řádové čárce s výkonem až 22,4 GFLOP/s na obvodu Xilinx KINTEX7 na prototypové desce KC705.
n4:tvurceVysledku
Kadlec, Jiří
n4:vlastnik
n6:vlastnikVysledku
n4:vyuzitiJinymSubjektem
n7:P