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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F12%3A00380442%21RIV13-MSM-67985556
rdf:type
n6:Vysledek skos:Concept
dcterms:description
The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table. The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table.
dcterms:title
Reducing Instruction Issue Overheads in Application-Specific Vector Processors Reducing Instruction Issue Overheads in Application-Specific Vector Processors
skos:prefLabel
Reducing Instruction Issue Overheads in Application-Specific Vector Processors Reducing Instruction Issue Overheads in Application-Specific Vector Processors
skos:notation
RIV/67985556:_____/12:00380442!RIV13-MSM-67985556
n6:predkladatel
n15:ico%3A67985556
n3:aktivita
n17:P
n3:aktivity
P(7H10001)
n3:dodaniDat
n10:2013
n3:domaciTvurceVysledku
n12:6719791 n12:7914571 n12:4505514 n12:4270320
n3:druhVysledku
n20:D
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n7:predkladatel
n3:idSjednocenehoVysledku
164483
n3:idVysledku
RIV/67985556:_____/12:00380442
n3:jazykVysledku
n19:eng
n3:klicovaSlova
custom accelerators; vector processing; FPGA; DSP
n3:klicoveSlovo
n5:DSP n5:custom%20accelerators n5:FPGA n5:vector%20processing
n3:kontrolniKodProRIV
[ED5F06249C81]
n3:mistoKonaniAkce
Cesme
n3:mistoVydani
Izmir
n3:nazevZdroje
Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012
n3:obor
n18:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
5
n3:projekt
n21:7H10001
n3:rokUplatneniVysledku
n10:2012
n3:tvurceVysledku
Sýkora, Jaroslav Honzík, P. Daněk, Martin Bartosinski, Roman Kohout, Lukáš
n3:typAkce
n11:WRD
n3:zahajeniAkce
2012-09-05+02:00
s:numberOfPages
8
n14:hasPublisher
Conference Publishing Services
n16:isbn
978-0-7695-4798-5