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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F12%3A00376595%21RIV13-MSM-67985556
rdf:type
n16:Vysledek skos:Concept
dcterms:description
The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology. The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology.
dcterms:title
The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor
skos:prefLabel
The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor
skos:notation
RIV/67985556:_____/12:00376595!RIV13-MSM-67985556
n16:predkladatel
n17:ico%3A67985556
n3:aktivita
n9:Z n9:P
n3:aktivity
P(7H10001), Z(AV0Z10750506)
n3:dodaniDat
n4:2013
n3:domaciTvurceVysledku
n13:2026449 n13:4270320 n13:6719791 n13:4505514 n13:7914571
n3:druhVysledku
n21:D
n3:duvernostUdaju
n8:S
n3:entitaPredkladatele
n15:predkladatel
n3:idSjednocenehoVysledku
123575
n3:idVysledku
RIV/67985556:_____/12:00376595
n3:jazykVysledku
n18:eng
n3:klicovaSlova
custom accelerators; vector processing; FPGA
n3:klicoveSlovo
n6:FPGA n6:custom%20accelerators n6:vector%20processing
n3:kontrolniKodProRIV
[936DCAEFF514]
n3:mistoKonaniAkce
Tallinn
n3:mistoVydani
Tallinn, ESTONIA
n3:nazevZdroje
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n19:JC
n3:pocetDomacichTvurcuVysledku
5
n3:pocetTvurcuVysledku
6
n3:projekt
n5:7H10001
n3:rokUplatneniVysledku
n4:2012
n3:tvurceVysledku
Sýkora, Jaroslav Kohout, Lukáš Daněk, Martin Honzík, P. Kafka, Leoš Bartosinski, Roman
n3:typAkce
n14:WRD
n3:wos
000312905700020
n3:zahajeniAkce
2012-04-18+02:00
n3:zamer
n22:AV0Z10750506
s:numberOfPages
6
n7:hasPublisher
IEEE
n20:isbn
978-1-4673-1185-4