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Namespace Prefixes

PrefixIRI
dctermshttp://purl.org/dc/terms/
n14http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n4http://linked.opendata.cz/resource/domain/vavai/projekt/
n10http://linked.opendata.cz/resource/domain/vavai/subjekt/
n9http://linked.opendata.cz/ontology/domain/vavai/
n16http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F67985556%3A_____%2F11%3A00380861%21RIV13-MSM-67985556/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n5http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n15http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n13http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n17http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n12http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F11%3A00380861%21RIV13-MSM-67985556
rdf:type
skos:Concept n9:Vysledek
dcterms:description
The article describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. An architecture of the developed processor is presented and its key blocks described - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPGAs. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is shown for a simple DSP computation typical for embedded systems. The article describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. An architecture of the developed processor is presented and its key blocks described - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPGAs. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is shown for a simple DSP computation typical for embedded systems.
dcterms:title
Hardware Support for Fine-Grain Multi-Threading in LEON3 Hardware Support for Fine-Grain Multi-Threading in LEON3
skos:prefLabel
Hardware Support for Fine-Grain Multi-Threading in LEON3 Hardware Support for Fine-Grain Multi-Threading in LEON3
skos:notation
RIV/67985556:_____/11:00380861!RIV13-MSM-67985556
n9:predkladatel
n10:ico%3A67985556
n3:aktivita
n15:P
n3:aktivity
P(7E08013)
n3:cisloPeriodika
1
n3:dodaniDat
n12:2013
n3:domaciTvurceVysledku
n14:2026449 n14:4270320 n14:4505514 n14:7914571
n3:druhVysledku
n17:J
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n16:predkladatel
n3:idSjednocenehoVysledku
201738
n3:idVysledku
RIV/67985556:_____/11:00380861
n3:jazykVysledku
n13:eng
n3:klicovaSlova
multithreading; microthreading; SPARC; microarchitecture; FPGA
n3:klicoveSlovo
n5:multithreading n5:SPARC n5:FPGA n5:microthreading n5:microarchitecture
n3:kodStatuVydavatele
RO - Rumunsko
n3:kontrolniKodProRIV
[058BAB1EAC73]
n3:nazevZdroje
Carpathian Journal of Electronic and Computer Engineering
n3:obor
n11:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n4:7E08013
n3:rokUplatneniVysledku
n12:2011
n3:svazekPeriodika
4
n3:tvurceVysledku
Daněk, Martin Kafka, Leoš Kohout, Lukáš Sýkora, Jaroslav
s:issn
1844-9689
s:numberOfPages
8