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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F11%3A00363078%21RIV12-AV0-67985556
rdf:type
skos:Concept n7:Vysledek
dcterms:description
The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform. The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.
dcterms:title
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
skos:prefLabel
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
skos:notation
RIV/67985556:_____/11:00363078!RIV12-AV0-67985556
n7:predkladatel
n8:ico%3A67985556
n3:aktivita
n20:P n20:Z
n3:aktivity
P(7H10001), Z(AV0Z10750506)
n3:dodaniDat
n9:2012
n3:domaciTvurceVysledku
n13:6719791
n3:druhVysledku
n12:D
n3:duvernostUdaju
n21:S
n3:entitaPredkladatele
n22:predkladatel
n3:idSjednocenehoVysledku
209083
n3:idVysledku
RIV/67985556:_____/11:00363078
n3:jazykVysledku
n16:eng
n3:klicovaSlova
LDU decomposition; directional forgetting; hardware accelerator
n3:klicoveSlovo
n4:hardware%20accelerator n4:LDU%20decomposition n4:directional%20forgetting
n3:kontrolniKodProRIV
[DBAF4B2513E8]
n3:mistoKonaniAkce
Praha
n3:mistoVydani
Praha
n3:nazevZdroje
ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing
n3:obor
n17:IN
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
1
n3:projekt
n10:7H10001
n3:rokUplatneniVysledku
n9:2011
n3:tvurceVysledku
Bartosinski, Roman
n3:typAkce
n11:WRD
n3:zahajeniAkce
2011-05-22+02:00
n3:zamer
n14:AV0Z10750506
s:numberOfPages
4
n18:hasPublisher
IEEE
n6:isbn
978-1-4577-0537-3