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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F11%3A00357150%21RIV11-MSM-67985556
rdf:type
skos:Concept n8:Vysledek
dcterms:description
We analyse an impact of long-latency instructions, the family blocksize parameter, and the thread switch modifier on execution efficiency of families of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor. The conclusions drawn in this paper can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor. We analyse an impact of long-latency instructions, the family blocksize parameter, and the thread switch modifier on execution efficiency of families of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor. The conclusions drawn in this paper can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor.
dcterms:title
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
skos:prefLabel
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
skos:notation
RIV/67985556:_____/11:00357150!RIV11-MSM-67985556
n8:predkladatel
n9:ico%3A67985556
n3:aktivita
n16:Z n16:P
n3:aktivity
P(7E08013), Z(AV0Z10750506)
n3:dodaniDat
n7:2011
n3:domaciTvurceVysledku
n5:2026449 n5:4270320 n5:4505514 n5:7914571
n3:druhVysledku
n22:D
n3:duvernostUdaju
n15:S
n3:entitaPredkladatele
n13:predkladatel
n3:idSjednocenehoVysledku
185655
n3:idVysledku
RIV/67985556:_____/11:00357150
n3:jazykVysledku
n6:eng
n3:klicovaSlova
Processor architectures; Multi-threading
n3:klicoveSlovo
n19:Multi-threading n19:Processor%20architectures
n3:kontrolniKodProRIV
[F94275215E2F]
n3:mistoKonaniAkce
Camo
n3:mistoVydani
Berlin
n3:nazevZdroje
Architecture of Computing Systems - ARCS 2011
n3:obor
n18:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n20:7E08013
n3:rokUplatneniVysledku
n7:2011
n3:tvurceVysledku
Kafka, Leoš Kohout, Lukáš Daněk, Martin Sýkora, Jaroslav
n3:typAkce
n4:WRD
n3:zahajeniAkce
2011-02-24+01:00
n3:zamer
n12:AV0Z10750506
s:numberOfPages
12
n21:hasPublisher
Springer-Verlag. (Berlin; Heidelberg)
n14:isbn
978-3-642-19136-7