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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F10%3A00342301%21RIV11-MSM-67985556
rdf:type
skos:Concept n15:Vysledek
dcterms:description
Embedded systems are getting more complex; that is why the high level of abstraction is required during the development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations have been implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method has been implemented. Embedded systems are getting more complex; that is why the high level of abstraction is required during the development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations have been implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method has been implemented.
dcterms:title
Reconfigurable Hardware Objects for Image Processing on FPGAs Reconfigurable Hardware Objects for Image Processing on FPGAs
skos:prefLabel
Reconfigurable Hardware Objects for Image Processing on FPGAs Reconfigurable Hardware Objects for Image Processing on FPGAs
skos:notation
RIV/67985556:_____/10:00342301!RIV11-MSM-67985556
n3:aktivita
n7:P n7:Z
n3:aktivity
P(7H09005), Z(AV0Z10750506)
n3:dodaniDat
n6:2011
n3:domaciTvurceVysledku
n8:1743961 n8:4270320 n8:4726731
n3:druhVysledku
n18:D
n3:duvernostUdaju
n11:S
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
284208
n3:idVysledku
RIV/67985556:_____/10:00342301
n3:jazykVysledku
n17:eng
n3:klicovaSlova
Image Processing; Reconfiguration; Hardware Object; FPGA
n3:klicoveSlovo
n4:FPGA n4:Reconfiguration n4:Image%20Processing n4:Hardware%20Object
n3:kontrolniKodProRIV
[F765F2AB50EB]
n3:mistoKonaniAkce
Vienna
n3:mistoVydani
Vienna
n3:nazevZdroje
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n13:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n5:7H09005
n3:rokUplatneniVysledku
n6:2010
n3:tvurceVysledku
Honzík, Petr Daněk, Martin Kloub, Jan
n3:typAkce
n20:EUR
n3:zahajeniAkce
2010-04-14+02:00
n3:zamer
n16:AV0Z10750506
s:numberOfPages
2
n12:hasPublisher
Institute of Electrical and Electronics Engineers
n19:isbn
978-1-4244-6610-8