This HTML5 document contains 49 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n16http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n19http://purl.org/net/nknouf/ns/bibtex#
n20http://linked.opendata.cz/resource/domain/vavai/projekt/
n15http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n8http://linked.opendata.cz/ontology/domain/vavai/
n14https://schema.org/
n10http://linked.opendata.cz/resource/domain/vavai/zamer/
n21http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F67985556%3A_____%2F10%3A00342262%21RIV11-MSM-67985556/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n4http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n5http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n13http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n17http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F10%3A00342262%21RIV11-MSM-67985556
rdf:type
n8:Vysledek skos:Concept
dcterms:description
This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems. This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems.
dcterms:title
Instruction Set Extensions for Multi-Threading in LEON3 Instruction Set Extensions for Multi-Threading in LEON3
skos:prefLabel
Instruction Set Extensions for Multi-Threading in LEON3 Instruction Set Extensions for Multi-Threading in LEON3
skos:notation
RIV/67985556:_____/10:00342262!RIV11-MSM-67985556
n3:aktivita
n9:P n9:Z
n3:aktivity
P(7E08013), Z(AV0Z10750506)
n3:dodaniDat
n17:2011
n3:domaciTvurceVysledku
n15:4505514 n15:4270320 n15:7914571 n15:2026449
n3:druhVysledku
n18:D
n3:duvernostUdaju
n5:S
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
264225
n3:idVysledku
RIV/67985556:_____/10:00342262
n3:jazykVysledku
n13:eng
n3:klicovaSlova
multithreading; instruction set extensions; microthreading; LEON3; SPARC; FPGA
n3:klicoveSlovo
n4:microthreading n4:instruction%20set%20extensions n4:LEON3 n4:SPARC n4:FPGA n4:multithreading
n3:kontrolniKodProRIV
[1F20D2B4C424]
n3:mistoKonaniAkce
Vídeň
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n7:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n20:7E08013
n3:rokUplatneniVysledku
n17:2010
n3:tvurceVysledku
Kohout, Lukáš Sýkora, Jaroslav Kafka, Leoš Daněk, Martin
n3:typAkce
n16:WRD
n3:zahajeniAkce
2010-04-14+02:00
n3:zamer
n10:AV0Z10750506
s:numberOfPages
6
n19:hasPublisher
IEEE
n14:isbn
978-1-4244-6610-8