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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F07%3A00090440%21RIV08-AV0-67985556
rdf:type
skos:Concept n18:Vysledek
dcterms:description
This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments. This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments. Tento článek popisuje metodu emulace, která zachovává strukturu a případně i časování emulovaného obvodu podle cílové technologie. Tato emulační metoda umožňuje použít metody vkládání poruch založené jak na modifikaci obvodu, tak na dynamické rekonfiguraci. Článek dále obsahuje výsledky několika experientů týkajících se této metody.
dcterms:title
Nová emulační metoda, která zachovává strukturu a časování obvodu A Novel Emulation Technique that Preserves Circuit Structure and Timing A Novel Emulation Technique that Preserves Circuit Structure and Timing
skos:prefLabel
A Novel Emulation Technique that Preserves Circuit Structure and Timing Nová emulační metoda, která zachovává strukturu a časování obvodu A Novel Emulation Technique that Preserves Circuit Structure and Timing
skos:notation
RIV/67985556:_____/07:00090440!RIV08-AV0-67985556
n3:strany
15;18
n3:aktivita
n8:Z n8:P
n3:aktivity
P(1QS108040510), Z(AV0Z10750506)
n3:dodaniDat
n9:2008
n3:domaciTvurceVysledku
n4:4270320 n4:2026449
n3:druhVysledku
n16:D
n3:duvernostUdaju
n7:S
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
408066
n3:idVysledku
RIV/67985556:_____/07:00090440
n3:jazykVysledku
n15:eng
n3:klicovaSlova
Fault emulation; FPGA; ASIC
n3:klicoveSlovo
n11:ASIC n11:Fault%20emulation n11:FPGA
n3:kontrolniKodProRIV
[D99B9EE433D0]
n3:mistoKonaniAkce
Tampere
n3:mistoVydani
Tampere
n3:nazevZdroje
International Symposium on System-on-Chip 2007 Proceedings
n3:obor
n14:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
3
n3:projekt
n13:1QS108040510
n3:rokUplatneniVysledku
n9:2007
n3:tvurceVysledku
Novák, O. Daněk, Martin Kafka, Leoš
n3:typAkce
n19:WRD
n3:zahajeniAkce
2007-11-20+01:00
n3:zamer
n17:AV0Z10750506
s:numberOfPages
4
n5:hasPublisher
IEEE
n20:isbn
1-4244-1367-2