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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F07%3A00080938%21RIV07-AV0-67985556
rdf:type
skos:Concept n16:Vysledek
dcterms:description
This application note describes accessory tools for partial dynamic reconfiguration on Xilinx FPGAs. These accessory tools deal with insertion of bus-macros. Basically the tools generate customized bus-macros and insert them to the top-level VHDL file that contains a module to be reconfigured. The idea is to relieve the end user of the tedious task currently carried out by hand. The tools are a complement to the Xilinx Partial Reconfiguration Early Access software tools (the PR tools). This application note describes accessory tools for partial dynamic reconfiguration on Xilinx FPGAs. These accessory tools deal with insertion of bus-macros. Basically the tools generate customized bus-macros and insert them to the top-level VHDL file that contains a module to be reconfigured. The idea is to relieve the end user of the tedious task currently carried out by hand. The tools are a complement to the Xilinx Partial Reconfiguration Early Access software tools (the PR tools). Tato technická zpráva popisuje pomocné nástroje pro částečnou dynamickou rekonfiguraci na FPGA firmy Xilinx. Nástroje umožňují automatické vkládáni bus-maker. Nástroje vytvoří nové bus-makro podle interface rekonfiguroveného modulu a vloží toto bus-makro do entity TOP. Oproti původnímu design flow tak není nutné provádět tyto operace ručně. Nástroje jsou doplňkem k balíčku nástrojů Xilinx Partial Reconfiguration Early Access software tools.
dcterms:title
Pomocné nástroje pro částečnou dynamickou rekonfiguraci na FPGA Xilinx Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs
skos:prefLabel
Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs Pomocné nástroje pro částečnou dynamickou rekonfiguraci na FPGA Xilinx
skos:notation
RIV/67985556:_____/07:00080938!RIV07-AV0-67985556
n3:aktivita
n9:P n9:Z
n3:aktivity
P(1QS108040510), Z(AV0Z10750506)
n3:dodaniDat
n14:2007
n3:domaciTvurceVysledku
n5:6719791 n5:2026449 n5:4270320
n3:druhVysledku
n12:A
n3:duvernostUdaju
n17:S
n3:entitaPredkladatele
n15:predkladatel
n3:idSjednocenehoVysledku
408368
n3:idVysledku
RIV/67985556:_____/07:00080938
n3:jazykVysledku
n13:eng
n3:klicovaSlova
FPGA; dynamic reconfiguration; VHDL
n3:klicoveSlovo
n8:VHDL n8:dynamic%20reconfiguration n8:FPGA
n3:kodPristupu
n11:L
n3:kontrolniKodProRIV
[07F458A509A7]
n3:mistoVydani
Praha
n3:obor
n7:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n18:1QS108040510
n3:rokUplatneniVysledku
n14:2007
n3:tvurceVysledku
Daněk, Martin Bartosinski, Roman Kafka, Leoš
n3:zamer
n4:AV0Z10750506