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Statements

Subject Item

n2:RIV%2F67985556%3A_____%2F06%3A00053712%21RIV07-MSM-67985556

rdf:type

skos:Concept n6:Vysledek

rdfs:seeAlso

zdenek.pohl@utia.cas.cz

dcterms:description

The functionality of FPGA RLS lattice filter implementation is demonstrated and archieved implementation parameters are provided. The functionality of FPGA RLS lattice filter implementation is demonstrated and archieved implementation parameters are provided. Dokument ukazuje funkci FPGA implementace RLS lattice filtru a shrnuje dosazené parametry.

dcterms:title

RLS Lattice Demo RLS Lattice Demo RLS Lattice Demo

skos:prefLabel

RLS Lattice Demo RLS Lattice Demo RLS Lattice Demo

skos:notation

RIV/67985556:_____/06:00053712!RIV07-MSM-67985556

n4:aktivita

n14:P

n4:aktivity

P(1M0567)

n4:dodaniDat

n17:2007

n4:domaciTvurceVysledku

n12:6386784 n12:8143404

n4:druhVysledku

n10:A

n4:duvernostUdaju

n15:S

n4:entitaPredkladatele

n13:predkladatel

n4:idSjednocenehoVysledku

497736

n4:idVysledku

RIV/67985556:_____/06:00053712

n4:jazykVysledku

n9:eng

n4:klicovaSlova

filtering; adaptive; FPGA; LNS

n4:klicoveSlovo

n7:LNS n7:adaptive n7:filtering n7:FPGA

n4:kodPristupu

n16:V

n4:kontrolniKodProRIV

[7DCBCBAD8BA7]

n4:mistoVydani

Praha

n4:obor

n5:IN

n4:pocetDomacichTvurcuVysledku

2

n4:pocetTvurcuVysledku

2

n4:projekt

n11:1M0567

n4:rokUplatneniVysledku

n17:2006

n4:tvurceVysledku

Pohl, Zdeněk Kadlec, Jiří