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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F06%3A00042476%21RIV10-AV0-67985556
rdf:type
skos:Concept n20:Vysledek
dcterms:description
The paper deals with floating-point-like implementation of the GSFAP algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz. The paper deals with floating-point-like implementation of the GSFAP algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz.
dcterms:title
FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic
skos:prefLabel
FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic
skos:notation
RIV/67985556:_____/06:00042476!RIV10-AV0-67985556
n4:aktivita
n10:Z
n4:aktivity
Z(AV0Z10750506)
n4:dodaniDat
n11:2010
n4:domaciTvurceVysledku
n18:2365030 n18:2751100
n4:druhVysledku
n14:D
n4:duvernostUdaju
n9:S
n4:entitaPredkladatele
n5:predkladatel
n4:idSjednocenehoVysledku
476258
n4:idVysledku
RIV/67985556:_____/06:00042476
n4:jazykVysledku
n17:eng
n4:klicovaSlova
adaptive filter; DSP; affine projection; logarithmic arithmetic; FPGA
n4:klicoveSlovo
n7:logarithmic%20arithmetic n7:DSP n7:affine%20projection n7:adaptive%20filter n7:FPGA
n4:kontrolniKodProRIV
[E7F0B593B2D4]
n4:mistoKonaniAkce
Banff
n4:mistoVydani
Calgary
n4:nazevZdroje
Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation
n4:obor
n15:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
3
n4:rokUplatneniVysledku
n11:2006
n4:tvurceVysledku
Gregg, D. Tichý, Milan Schier, Jan
n4:typAkce
n6:WRD
n4:zahajeniAkce
2006-10-02+02:00
n4:zamer
n12:AV0Z10750506
s:numberOfPages
6
n16:hasPublisher
IEEE Signal Processing Society
n19:isbn
978-1-4244-0382-0