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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F05%3A00411508%21RIV10-MSM-67985556
rdf:type
skos:Concept n20:Vysledek
dcterms:description
Optimization of an FPGA implementation of iterative algorithms with nested loops is treated, using Integer Linear Programming. An example of the FI-CMA blind equalization algorithm is considered, using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. An optimally scheduled abstract model is constructed, modeling imperfectly nested loops. Optimization of an FPGA implementation of iterative algorithms with nested loops is treated, using Integer Linear Programming. An example of the FI-CMA blind equalization algorithm is considered, using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. An optimally scheduled abstract model is constructed, modeling imperfectly nested loops.
dcterms:title
Optimization of finite interval CMA implementation for FPGA Optimization of finite interval CMA implementation for FPGA
skos:prefLabel
Optimization of finite interval CMA implementation for FPGA Optimization of finite interval CMA implementation for FPGA
skos:notation
RIV/67985556:_____/05:00411508!RIV10-MSM-67985556
n4:aktivita
n6:Z n6:P
n4:aktivity
P(1ET300750402), P(1M0567), Z(AV0Z10750506)
n4:dodaniDat
n13:2010
n4:domaciTvurceVysledku
n17:2365030 n17:2584026
n4:druhVysledku
n15:D
n4:duvernostUdaju
n5:S
n4:entitaPredkladatele
n19:predkladatel
n4:idSjednocenehoVysledku
534891
n4:idVysledku
RIV/67985556:_____/05:00411508
n4:jazykVysledku
n12:eng
n4:klicovaSlova
CMA; FPGA; logarithmic arithmetic; cyclic scheduling
n4:klicoveSlovo
n10:FPGA n10:logarithmic%20arithmetic n10:CMA n10:cyclic%20scheduling
n4:kontrolniKodProRIV
[74F894787274]
n4:mistoKonaniAkce
Athens
n4:mistoVydani
Athens
n4:nazevZdroje
Proceedings of the IEEE Workshop on Signal Processing Systems. SiPS 2005
n4:obor
n11:BD
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
4
n4:projekt
n9:1ET300750402 n9:1M0567
n4:rokUplatneniVysledku
n13:2005
n4:tvurceVysledku
Heřmánek, Antonín Šůcha, P. Hanzálek, Z. Schier, Jan
n4:typAkce
n21:WRD
n4:zahajeniAkce
2005-11-02+01:00
n4:zamer
n8:AV0Z10750506
s:numberOfPages
7
n18:hasPublisher
IEEE
n16:isbn
0-7803-9333-3