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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F05%3A00411312%21RIV10-AV0-67985556
rdf:type
skos:Concept n21:Vysledek
dcterms:description
An FPGA implementation of the FI-CMA algorithm using the Virtex-E and Virtex-II devices is presented. The algorithm consists of two parts: one, performing batch-QR decomposition of the data matrix, and second, used for an iterative equalizer optimization, using the columns of the Q-matrix as input. The resource reuse and minimization of the total latency have been emphasized. Logarithmic arithmetic library has been used for floating point calculations, required in algorithm. An FPGA implementation of the FI-CMA algorithm using the Virtex-E and Virtex-II devices is presented. The algorithm consists of two parts: one, performing batch-QR decomposition of the data matrix, and second, used for an iterative equalizer optimization, using the columns of the Q-matrix as input. The resource reuse and minimization of the total latency have been emphasized. Logarithmic arithmetic library has been used for floating point calculations, required in algorithm.
dcterms:title
FPGA implementation of Finite Interval CMA FPGA implementation of Finite Interval CMA
skos:prefLabel
FPGA implementation of Finite Interval CMA FPGA implementation of Finite Interval CMA
skos:notation
RIV/67985556:_____/05:00411312!RIV10-AV0-67985556
n3:aktivita
n7:P n7:Z
n3:aktivity
P(1ET300750402), Z(AV0Z10750506)
n3:dodaniDat
n17:2010
n3:domaciTvurceVysledku
n11:2365030 n11:2584026
n3:druhVysledku
n19:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n14:predkladatel
n3:idSjednocenehoVysledku
522033
n3:idVysledku
RIV/67985556:_____/05:00411312
n3:jazykVysledku
n20:eng
n3:klicovaSlova
CMA algorithm; FPGA; data matrix
n3:klicoveSlovo
n8:FPGA n8:data%20matrix n8:CMA%20algorithm
n3:kontrolniKodProRIV
[2A619F235F7F]
n3:mistoKonaniAkce
Antverpy
n3:mistoVydani
Antverpy
n3:nazevZdroje
Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005
n3:obor
n18:JA
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n16:1ET300750402
n3:rokUplatneniVysledku
n17:2005
n3:tvurceVysledku
Schier, Jan Heřmánek, Antonín
n3:typAkce
n6:EUR
n3:zahajeniAkce
2005-04-19+02:00
n3:zamer
n15:AV0Z10750506
s:numberOfPages
3
n13:hasPublisher
IEEE
n5:isbn
0-7803-9333-3