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Statements

Subject Item
n2:RIV%2F67985556%3A_____%2F04%3A00106325%21RIV%2F2005%2FMSM%2FA16005%2FN
rdf:type
n18:Vysledek skos:Concept
dcterms:description
In the paper, we present the architecture design of the Finite Interval Constant Modulus Algorithm (FI-CMA) for FPGA implementation. For floating point calculations required in the algorithm we use the library based on the Logarithmic Number System (LNS). In the design, the resource reuse and minimization of the total latency is emphasized. In the paper, we present the architecture design of the Finite Interval Constant Modulus Algorithm (FI-CMA) for FPGA implementation. For floating point calculations required in the algorithm we use the library based on the Logarithmic Number System (LNS). In the design, the resource reuse and minimization of the total latency is emphasized. V článku je prezentován návrh architektury pro FPGA implementaci blokového CMA algoritmu. Pro výpočty v plovoucí řádové čárce, požadované v tomto algoritmu, byla použita aritmetická knihovna využívající logaritmickou číselnou soustavu. Návrh architektury je optimalizován pro vícenásobné využití HW prostředků a minimalizaci celkové latence
dcterms:title
Návrh architektury pro FPGA implementaci blokového CMA algoritmu (Finite interval CMA) Architecture design for FPGA implementation of finite interval CMA Architecture design for FPGA implementation of finite interval CMA
skos:prefLabel
Architecture design for FPGA implementation of finite interval CMA Návrh architektury pro FPGA implementaci blokového CMA algoritmu (Finite interval CMA) Architecture design for FPGA implementation of finite interval CMA
skos:notation
RIV/67985556:_____/04:00106325!RIV/2005/MSM/A16005/N
n3:strany
1;4
n3:aktivita
n14:P n14:Z
n3:aktivity
P(1ET300750402), P(1ET400750408), P(LN00B096), Z(AV0Z1075907)
n3:dodaniDat
n4:2005
n3:domaciTvurceVysledku
n13:2584026 n13:2365030
n3:druhVysledku
n9:D
n3:duvernostUdaju
n17:S
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
555322
n3:idVysledku
RIV/67985556:_____/04:00106325
n3:jazykVysledku
n10:eng
n3:klicovaSlova
blind equalization;CMA, FPGA;logarithmic arithmetic
n3:klicoveSlovo
n6:blind%20equalization n6:logarithmic%20arithmetic n6:CMA n6:FPGA
n3:kontrolniKodProRIV
[7246FBEF7DEA]
n3:mistoKonaniAkce
Vienna
n3:mistoVydani
Vienna
n3:nazevZdroje
Proceedings of the 12th European Signal Processing Conference
n3:obor
n20:BD
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
3
n3:projekt
n7:LN00B096 n7:1ET400750408 n7:1ET300750402
n3:rokUplatneniVysledku
n4:2004
n3:tvurceVysledku
Regalia, P. Schier, Jan Heřmánek, Antonín
n3:typAkce
n15:EUR
n3:zahajeniAkce
2004-09-06+02:00
n3:zamer
n5:AV0Z1075907
s:numberOfPages
4
n11:hasPublisher
University of Technology
n19:isbn
3-200-00165-8