This HTML5 document contains 47 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n4http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n19http://purl.org/net/nknouf/ns/bibtex#
n6http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n5http://linked.opendata.cz/resource/domain/vavai/projekt/
n9http://linked.opendata.cz/ontology/domain/vavai/
n15https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n13http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F63839172%3A_____%2F14%3A10130393%21RIV15-MSM-63839172/
n12http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n20http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n17http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n10http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F63839172%3A_____%2F14%3A10130393%21RIV15-MSM-63839172
rdf:type
n9:Vysledek skos:Concept
dcterms:description
Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security threats. We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. The concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or Cyclone V) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100 Gb/s flow traffic measurement augmented by a selected application protocol analysis. Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security threats. We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. The concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or Cyclone V) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100 Gb/s flow traffic measurement augmented by a selected application protocol analysis.
dcterms:title
Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring
skos:prefLabel
Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring
skos:notation
RIV/63839172:_____/14:10130393!RIV15-MSM-63839172
n3:aktivita
n20:S n20:P
n3:aktivity
P(ED1.1.00/02.0070), P(LM2010005), S
n3:dodaniDat
n10:2015
n3:domaciTvurceVysledku
n6:9452591 n6:6647596 n6:8405158
n3:druhVysledku
n11:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n13:predkladatel
n3:idSjednocenehoVysledku
50908
n3:idVysledku
RIV/63839172:_____/14:10130393
n3:jazykVysledku
n7:eng
n3:klicovaSlova
L7; Application protocols; Acceleration; Monitoring; FPGA
n3:klicoveSlovo
n12:Application%20protocols n12:L7 n12:Monitoring n12:FPGA n12:Acceleration
n3:kontrolniKodProRIV
[27C1B155674F]
n3:mistoKonaniAkce
Munich, Germany
n3:mistoVydani
Munich, Germany
n3:nazevZdroje
2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014)
n3:obor
n17:IN
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
4
n3:projekt
n5:LM2010005 n5:ED1.1.00%2F02.0070
n3:rokUplatneniVysledku
n10:2014
n3:tvurceVysledku
Puš, Viktor Benáček, Pavel Kořenek, Jan Kekely, Lukáš
n3:typAkce
n4:WRD
n3:zahajeniAkce
2014-09-02+02:00
s:numberOfPages
4
n19:hasPublisher
IEEE Circuits and Systems Society
n15:isbn
978-3-00-044645-0