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Statements

Subject Item
n2:RIV%2F63839172%3A_____%2F14%3A10130332%21RIV15-MSM-63839172
rdf:type
skos:Concept n10:Vysledek
dcterms:description
Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols. Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.
dcterms:title
Design Methodology of Configurable High Performance Packet Parser for FPGA Design Methodology of Configurable High Performance Packet Parser for FPGA
skos:prefLabel
Design Methodology of Configurable High Performance Packet Parser for FPGA Design Methodology of Configurable High Performance Packet Parser for FPGA
skos:notation
RIV/63839172:_____/14:10130332!RIV15-MSM-63839172
n4:aktivita
n14:S n14:P
n4:aktivity
P(ED1.1.00/02.0070), P(LM2010005), S
n4:dodaniDat
n8:2015
n4:domaciTvurceVysledku
n5:9452591 n5:8405158 n5:6647596
n4:druhVysledku
n19:D
n4:duvernostUdaju
n11:S
n4:entitaPredkladatele
n7:predkladatel
n4:idSjednocenehoVysledku
10439
n4:idVysledku
RIV/63839172:_____/14:10130332
n4:jazykVysledku
n20:eng
n4:klicovaSlova
FPGA; Latency; Packet Parsing
n4:klicoveSlovo
n6:FPGA n6:Latency n6:Packet%20Parsing
n4:kontrolniKodProRIV
[FF747A4223DA]
n4:mistoKonaniAkce
Warsaw, Poland
n4:mistoVydani
Warsaw, Poland
n4:nazevZdroje
2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
n4:obor
n17:IN
n4:pocetDomacichTvurcuVysledku
3
n4:pocetTvurcuVysledku
3
n4:projekt
n13:LM2010005 n13:ED1.1.00%2F02.0070
n4:rokUplatneniVysledku
n8:2014
n4:tvurceVysledku
Puš, Viktor Kořenek, Jan Kekely, Lukáš
n4:typAkce
n12:WRD
n4:wos
000346734200038
n4:zahajeniAkce
2014-04-22+02:00
s:issn
2334-3133
s:numberOfPages
6
n9:hasPublisher
IEEE Computer Society
n15:isbn
978-1-4799-4558-0