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Statements

Subject Item
n2:RIV%2F63839172%3A_____%2F13%3A10130355%21RIV14-MSM-63839172
rdf:type
skos:Concept n16:Vysledek
rdfs:seeAlso
http://www.cesnet.cz/wp-content/uploads/2014/02/card.pdf
dcterms:description
This technical report describes the design of hardware accelerator for 100G Ethernet network security monitoring. The hardware is a PCI Express gen3 X16 board with a single 100G optical Ethernet interface and uses the Virtex-7 FPGA. In addition to the hardware, the report also presents some important blocks of the FPGA firmware: 100G Ethernet block and the NetCOPE Development Platform. The hardware, together with some additional firmware and software is intended to be used for the CESNET2 network border lines security monitoring. This technical report describes the design of hardware accelerator for 100G Ethernet network security monitoring. The hardware is a PCI Express gen3 X16 board with a single 100G optical Ethernet interface and uses the Virtex-7 FPGA. In addition to the hardware, the report also presents some important blocks of the FPGA firmware: 100G Ethernet block and the NetCOPE Development Platform. The hardware, together with some additional firmware and software is intended to be used for the CESNET2 network border lines security monitoring.
dcterms:title
Designing a Card for 100 Gb/s Network Monitoring Designing a Card for 100 Gb/s Network Monitoring
skos:prefLabel
Designing a Card for 100 Gb/s Network Monitoring Designing a Card for 100 Gb/s Network Monitoring
skos:notation
RIV/63839172:_____/13:10130355!RIV14-MSM-63839172
n16:predkladatel
n17:ico%3A63839172
n3:aktivita
n12:P
n3:aktivity
P(LM2010005)
n3:dodaniDat
n4:2014
n3:domaciTvurceVysledku
n11:8813124 n11:6647596 n11:3339807 n11:9461728
n3:druhVysledku
n18:A
n3:duvernostUdaju
n9:S
n3:entitaPredkladatele
n10:predkladatel
n3:idSjednocenehoVysledku
68664
n3:idVysledku
RIV/63839172:_____/13:10130355
n3:jazykVysledku
n15:eng
n3:klicovaSlova
SDM; NetCOPE; security; monitoring; FPGA; Ethernet; 100GE
n3:klicoveSlovo
n8:monitoring n8:Ethernet n8:FPGA n8:NetCOPE n8:SDM n8:100GE n8:security
n3:kodPristupu
n6:V
n3:kontrolniKodProRIV
[F19EB224E122]
n3:mistoVydani
Praha
n3:objednatelVyzkumneZpravy
CESNET
n3:obor
n19:IN
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n7:LM2010005
n3:rokUplatneniVysledku
n4:2013
n3:tvurceVysledku
Špinler, Martin Puš, Viktor Friedl, Štěpán Matoušek, Jiří