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Statements

Subject Item
n2:RIV%2F63839172%3A_____%2F10%3A00006989%21RIV11-MSM-63839172
rdf:type
n9:Vysledek skos:Concept
dcterms:description
Many hardware architectures have been designed to accelerate regular expression matching in network security devices, but most of them can achieve high throughput only for strings or small sets of regular expressions. We propose new NFA Split architecture which reduces the amount of consumed FPGA resources in order to match larger set of regular expressions. New algorithm is introduced to find non-collision sets of states and determine part of nondeterministic automaton which can be mapped to the memory based architecture. For all analysed sets of regular expressions, the algorithm was able to find non-collision sets with 67.8 % of states in average and reduces the amount of consumed flip-flops to 37.6 % and look-up tables to 63.9 % in average. Many hardware architectures have been designed to accelerate regular expression matching in network security devices, but most of them can achieve high throughput only for strings or small sets of regular expressions. We propose new NFA Split architecture which reduces the amount of consumed FPGA resources in order to match larger set of regular expressions. New algorithm is introduced to find non-collision sets of states and determine part of nondeterministic automaton which can be mapped to the memory based architecture. For all analysed sets of regular expressions, the algorithm was able to find non-collision sets with 67.8 % of states in average and reduces the amount of consumed flip-flops to 37.6 % and look-up tables to 63.9 % in average.
dcterms:title
NFA Split Architecture for Fast Regular Expression Matching NFA Split Architecture for Fast Regular Expression Matching
skos:prefLabel
NFA Split Architecture for Fast Regular Expression Matching NFA Split Architecture for Fast Regular Expression Matching
skos:notation
RIV/63839172:_____/10:00006989!RIV11-MSM-63839172
n4:aktivita
n14:Z
n4:aktivity
Z(MSM6383917201)
n4:dodaniDat
n19:2011
n4:domaciTvurceVysledku
n17:9452591
n4:druhVysledku
n7:D
n4:duvernostUdaju
n16:S
n4:entitaPredkladatele
n18:predkladatel
n4:idSjednocenehoVysledku
274865
n4:idVysledku
RIV/63839172:_____/10:00006989
n4:jazykVysledku
n11:eng
n4:klicovaSlova
Hledání regulárních výrazů; Automat; FPGA
n4:klicoveSlovo
n8:Hled%C3%A1n%C3%AD%20regul%C3%A1rn%C3%ADch%20v%C3%BDraz%C5%AF n8:Automat n8:FPGA
n4:kontrolniKodProRIV
[1C132C8AD110]
n4:mistoKonaniAkce
La Jolla, US
n4:mistoVydani
La Jolla, US
n4:nazevZdroje
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
n4:obor
n13:IN
n4:pocetDomacichTvurcuVysledku
1
n4:pocetTvurcuVysledku
2
n4:rokUplatneniVysledku
n19:2010
n4:tvurceVysledku
Košař, Vlastimil Kořenek, Jan
n4:typAkce
n6:WRD
n4:zahajeniAkce
2010-01-01+01:00
n4:zamer
n12:MSM6383917201
s:numberOfPages
2
n10:hasPublisher
Neuveden
n20:isbn
978-1-4503-0379-8