This HTML5 document contains 46 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n9http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F61989100%3A27740%2F13%3A86087301%21RIV14-MSM-27740___/
dctermshttp://purl.org/dc/terms/
n12http://localhost/temp/predkladatel/
n17http://linked.opendata.cz/resource/domain/vavai/subjekt/
n16http://linked.opendata.cz/ontology/domain/vavai/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n14http://bibframe.org/vocab/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n7http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n13http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n18http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n15http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n4http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F61989100%3A27740%2F13%3A86087301%21RIV14-MSM-27740___
rdf:type
skos:Concept n16:Vysledek
dcterms:description
In current era of complex chip designs targeting wireless mobile terminals, architects and designers need to conform to tight design constraints – both in terms of performance (e.g. execution time, silicon area, energy consumption) and time-to-market. Further, additional flexibility is required in these designs to handle multiple wireless standards, sometimes even concurrently. To achieve these challenging goals, the authors introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. The authors demonstrate three main achievements in running multiple wireless standards on their platform: 1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 3GPP-LTE one in 52µs. Further the authors describe the design flow used to prepare main components of our platform architecture for a tape-out, while especially keeping a close eye on energy consumption. We believe that our chip design flow is generic and can be used in other custom processor chip designs even outside wireless domain. In current era of complex chip designs targeting wireless mobile terminals, architects and designers need to conform to tight design constraints – both in terms of performance (e.g. execution time, silicon area, energy consumption) and time-to-market. Further, additional flexibility is required in these designs to handle multiple wireless standards, sometimes even concurrently. To achieve these challenging goals, the authors introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. The authors demonstrate three main achievements in running multiple wireless standards on their platform: 1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 3GPP-LTE one in 52µs. Further the authors describe the design flow used to prepare main components of our platform architecture for a tape-out, while especially keeping a close eye on energy consumption. We believe that our chip design flow is generic and can be used in other custom processor chip designs even outside wireless domain.
dcterms:title
Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication
skos:prefLabel
Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication
skos:notation
RIV/61989100:27740/13:86087301!RIV14-MSM-27740___
n16:predkladatel
n17:orjk%3A27740
n3:aktivita
n18:N
n3:aktivity
N
n3:cisloPeriodika
1
n3:dodaniDat
n4:2014
n3:domaciTvurceVysledku
Palkovič, Martin
n3:druhVysledku
n15:J
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n9:predkladatel
n3:idSjednocenehoVysledku
68577
n3:idVysledku
RIV/61989100:27740/13:86087301
n3:jazykVysledku
n8:eng
n3:klicovaSlova
WLAN; LTE; Platform Architecture Design; Design Flow; Wireless Systems
n3:klicoveSlovo
n7:Design%20Flow n7:Platform%20Architecture%20Design n7:WLAN n7:Wireless%20Systems n7:LTE
n3:kodStatuVydavatele
US - Spojené státy americké
n3:kontrolniKodProRIV
[F0AD66A5EC42]
n3:nazevZdroje
International Journal of Embedded and Real-Time Communication Systems
n3:obor
n11:JA
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
7
n3:rokUplatneniVysledku
n4:2013
n3:svazekPeriodika
4
n3:tvurceVysledku
Amin, Amir Avasare, Prabhat Declerck, Jeroen Umans, Erik Glassee, Miguel Raghavan, Praveen Palkovič, Martin
s:issn
1947-3176
s:numberOfPages
21
n14:doi
10.4018/jertcs.2013010103
n12:organizacniJednotka
27740