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Statements

Subject Item
n2:RIV%2F61989100%3A27240%2F14%3A86093022%21RIV15-MSM-27240___
rdf:type
n5:Vysledek skos:Concept
dcterms:description
In this paper, we propose a parallel processing model based on systolic computing merged with concepts of evolutionary algorithms. The proposed model works over a Graphics Processing Unit using the structure of threads as cells that form a systolic mesh. Data passes through those cells, each one performing a simple computing operation. The systolic algorithm is implemented using NVIDIA's compute unified device architecture. To investigate the behavior and performance of the proposed model we test it over a NP-complete problem. The study of systolic algorithms on GPU and the different versions of the proposal show that our canonical model is a competitive solver with efficacy and presents a good scalability behavior across different instance sizes. 2013 Springer-Verlag Berlin Heidelberg. In this paper, we propose a parallel processing model based on systolic computing merged with concepts of evolutionary algorithms. The proposed model works over a Graphics Processing Unit using the structure of threads as cells that form a systolic mesh. Data passes through those cells, each one performing a simple computing operation. The systolic algorithm is implemented using NVIDIA's compute unified device architecture. To investigate the behavior and performance of the proposed model we test it over a NP-complete problem. The study of systolic algorithms on GPU and the different versions of the proposal show that our canonical model is a competitive solver with efficacy and presents a good scalability behavior across different instance sizes. 2013 Springer-Verlag Berlin Heidelberg.
dcterms:title
Systolic neighborhood search on graphics processing units Systolic neighborhood search on graphics processing units
skos:prefLabel
Systolic neighborhood search on graphics processing units Systolic neighborhood search on graphics processing units
skos:notation
RIV/61989100:27240/14:86093022!RIV15-MSM-27240___
n3:aktivita
n11:S
n3:aktivity
S
n3:cisloPeriodika
1
n3:dodaniDat
n15:2015
n3:domaciTvurceVysledku
Alba, Enrique
n3:druhVysledku
n13:J
n3:duvernostUdaju
n9:S
n3:entitaPredkladatele
n16:predkladatel
n3:idSjednocenehoVysledku
49238
n3:idVysledku
RIV/61989100:27240/14:86093022
n3:jazykVysledku
n12:eng
n3:klicovaSlova
Systolic architecture; Parallel computing; Optimization; Evolutionary algorithm; CUDA
n3:klicoveSlovo
n7:Optimization n7:Systolic%20architecture n7:Parallel%20computing n7:Evolutionary%20algorithm n7:CUDA
n3:kodStatuVydavatele
US - Spojené státy americké
n3:kontrolniKodProRIV
[D4862678AD86]
n3:nazevZdroje
Soft computing
n3:obor
n6:IN
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n15:2014
n3:svazekPeriodika
18
n3:tvurceVysledku
Vidal, Pablo Alba, Enrique Luna, Francisco
n3:wos
000329247000010
s:issn
1432-7643
s:numberOfPages
18
n17:doi
10.1007/s00500-013-1041-7
n14:organizacniJednotka
27240