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Statements

Subject Item
n2:RIV%2F49777513%3A23220%2F14%3A43923594%21RIV15-MSM-23220___
rdf:type
skos:Concept n13:Vysledek
dcterms:description
Digital filters are necessary in digital transmitter / receiver side and popularity of Software Defined Radio (SDR) is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. The goal of this paper is to develop efficient pipelined polyphase FIR filter structures in VHDL language for RTL synthesis on FPGA. The proposed structures contain fully parallel polyphase decimation and interpolation FIR filter models. The first part of this paper is focused on formulation of distributed arithmetic technique with polyphase decomposition, which represents the core of designed models. The second part describes mentioned polyphase FIR VHDL models. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size balance. The third part of this paper deals with rapid design and simulation of proposed VHDL models. The result of RTL synthesis is finally discussed. Very good performance and optimal design size are main benefits of proposed polyphase FIR filters. Developed structures are very suitable for multichannel operation in digital I/Q receiver. Digital filters are necessary in digital transmitter / receiver side and popularity of Software Defined Radio (SDR) is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. The goal of this paper is to develop efficient pipelined polyphase FIR filter structures in VHDL language for RTL synthesis on FPGA. The proposed structures contain fully parallel polyphase decimation and interpolation FIR filter models. The first part of this paper is focused on formulation of distributed arithmetic technique with polyphase decomposition, which represents the core of designed models. The second part describes mentioned polyphase FIR VHDL models. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size balance. The third part of this paper deals with rapid design and simulation of proposed VHDL models. The result of RTL synthesis is finally discussed. Very good performance and optimal design size are main benefits of proposed polyphase FIR filters. Developed structures are very suitable for multichannel operation in digital I/Q receiver.
dcterms:title
High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA
skos:prefLabel
High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA
skos:notation
RIV/49777513:23220/14:43923594!RIV15-MSM-23220___
n3:aktivita
n4:S
n3:aktivity
S
n3:dodaniDat
n9:2015
n3:domaciTvurceVysledku
n15:6052460 n15:8823693
n3:druhVysledku
n18:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n17:predkladatel
n3:idSjednocenehoVysledku
19074
n3:idVysledku
RIV/49777513:23220/14:43923594
n3:jazykVysledku
n19:eng
n3:klicovaSlova
VHDL; polyphase; signal; SDR; FPGA; FIR filters; digital signal processing
n3:klicoveSlovo
n7:VHDL n7:SDR n7:polyphase n7:FIR%20filters n7:FPGA n7:digital%20signal%20processing n7:signal
n3:kontrolniKodProRIV
[F56FBB3F3940]
n3:mistoKonaniAkce
Plzeň
n3:mistoVydani
Plzeň
n3:nazevZdroje
2014 International Conference on Applied Electronics
n3:obor
n14:JA
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:rokUplatneniVysledku
n9:2014
n3:tvurceVysledku
Fiala, Pavel Linhart, Richard
n3:typAkce
n11:WRD
n3:zahajeniAkce
2014-09-09+02:00
s:issn
1803-7232
s:numberOfPages
4
n6:hasPublisher
Západočeská univerzita v Plzni
n20:isbn
978-80-261-0276-2
n12:organizacniJednotka
23220