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Statements

Subject Item
n2:RIV%2F49777513%3A23220%2F03%3A00000027%21RIV%2F2004%2FMSM%2F232204%2FN
rdf:type
n9:Vysledek skos:Concept
dcterms:description
This paper describes a new architecture of a digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other methods. Presented synthesizer is the most suitable for the design of VLSI a rchitectures or for programmable logical devices (CPLD, FPGA). This synthesizer has a disadvantage in low output frequency, which can be overcome by using this synthesizer together with phase-locked loop. This paper describes a new architecture of a digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other methods. Presented synthesizer is the most suitable for the design of VLSI a rchitectures or for programmable logical devices (CPLD, FPGA). This synthesizer has a disadvantage in low output frequency, which can be overcome by using this synthesizer together with phase-locked loop.
dcterms:title
FPGA realization of the digital frequency synthesizer FPGA realization of the digital frequency synthesizer
skos:prefLabel
FPGA realization of the digital frequency synthesizer FPGA realization of the digital frequency synthesizer
skos:notation
RIV/49777513:23220/03:00000027!RIV/2004/MSM/232204/N
n3:strany
205-207
n3:aktivita
n16:P
n3:aktivity
P(LN00B084)
n3:dodaniDat
n7:2004
n3:domaciTvurceVysledku
n15:6631959 n15:4844556
n3:druhVysledku
n19:D
n3:duvernostUdaju
n11:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
607658
n3:idVysledku
RIV/49777513:23220/03:00000027
n3:jazykVysledku
n21:eng
n3:klicovaSlova
FPGA;digital frequency synthesizer;direct digital synthesis;phase-locked loop
n3:klicoveSlovo
n6:phase-locked%20loop n6:FPGA n6:digital%20frequency%20synthesizer n6:direct%20digital%20synthesis
n3:kontrolniKodProRIV
[94E88263A4AC]
n3:mistoKonaniAkce
ZČU FEL Plzeň
n3:mistoVydani
Pilsen
n3:nazevZdroje
Applied Electronics 2003
n3:obor
n10:JA
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:pocetUcastnikuAkce
0
n3:pocetZahranicnichUcastnikuAkce
0
n3:projekt
n4:LN00B084
n3:rokUplatneniVysledku
n7:2003
n3:tvurceVysledku
Klusal, Miloš Štork, Milan
n3:typAkce
n20:WRD
n3:zahajeniAkce
2003-09-10+02:00
s:numberOfPages
3
n14:hasPublisher
Západočeská univerzita v Plzni
n8:isbn
80-7082-951-6
n17:organizacniJednotka
23220