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Statements

Subject Item
n2:RIV%2F46747885%3A24220%2F99%3A00000048%21RIV%2F2000%2FMSM%2F242200
rdf:type
skos:Concept n13:Vysledek
dcterms:description
The paper presents a design method for Built-In Self Test (BIST) that uses a cellular automaton (CA) for test pattern generation. Similarly to the test pattern generators with linear feedback shift registers (LFSR) the CA can generate pseudorandom test patterns. The patterns correspond to code words or to linear combination of different code words of codes with non primitive irreducible polynomials and with higher minimal code distance of its dual code. The CA is formed by T flip-flops and does not contain any XOR in the feedback. We proposed a new scheme of BIST where the CA is formed by a modified scan chain. A number of experiments were done with ISCAS 85 and 89 benchmark circuits. The achieved fault coverage is better than that obtained with the help of patterns generated by LFSRs. The paper presents a design method for Built-In Self Test (BIST) that uses a cellular automaton (CA) for test pattern generation. Similarly to the test pattern generators with linear feedback shift registers (LFSR) the CA can generate pseudorandom test patterns. The patterns correspond to code words or to linear combination of different code words of codes with non primitive irreducible polynomials and with higher minimal code distance of its dual code. The CA is formed by T flip-flops and does not contain any XOR in the feedback. We proposed a new scheme of BIST where the CA is formed by a modified scan chain. A number of experiments were done with ISCAS 85 and 89 benchmark circuits. The achieved fault coverage is better than that obtained with the help of patterns generated by LFSRs.
dcterms:title
Random-Pattern Coverage Enhancement for BIST Random-Pattern Coverage Enhancement for BIST
skos:prefLabel
Random-Pattern Coverage Enhancement for BIST Random-Pattern Coverage Enhancement for BIST
skos:notation
RIV/46747885:24220/99:00000048!RIV/2000/MSM/242200
n4:strany
nečíslová
n4:aktivita
n16:Z n16:P
n4:aktivity
P(GA102/98/1003), P(VS96006), Z(MSM 242200002)
n4:dodaniDat
n14:2000
n4:domaciTvurceVysledku
Novák, Ondřej
n4:druhVysledku
n12:D
n4:duvernostUdaju
n7:S
n4:entitaPredkladatele
n6:predkladatel
n4:idSjednocenehoVysledku
751946
n4:idVysledku
RIV/46747885:24220/99:00000048
n4:jazykVysledku
n5:eng
n4:kontrolniKodProRIV
[9B53801D9A9E]
n4:mistoVydani
Německo
n4:nazevZdroje
Proceedings of IEEE European Test Workshop
n4:obor
n9:JC
n4:pocetDomacichTvurcuVysledku
1
n4:pocetTvurcuVysledku
1
n4:projekt
n11:GA102%2F98%2F1003 n11:VS96006
n4:rokUplatneniVysledku
n14:1999
n4:tvurceVysledku
Novák, Ondřej
n4:zamer
n15:MSM%20242200002
s:numberOfPages
2
n17:hasPublisher
IEEE
n18:organizacniJednotka
24220